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1. 发明授权

US10237059B2 Diversified instruction set processing to enhance security 有权
公开(公告)号：US10237059B2
公开(公告)日：2019-03-19
申请号：US14946961
申请日：2015-11-20
申请人： Lakshminarasimhan Sethumadhavan , Kanad Sinha , Angelos Keromytis , Vasileios Pappas , Vasileios Kemerlis
发明人： Lakshminarasimhan Sethumadhavan , Kanad Sinha , Angelos Keromytis , Vasileios Pappas , Vasileios Kemerlis
IPC分类号： G06F12/14 , H04L29/06 , H04L9/08 , H04L9/00 , H04L9/28 , G06F21/72 , G06F9/30 , G06F12/0897 , G06F21/12 , G06F21/57
摘要： Disclosed are devices, systems, apparatus, methods, products, and other implementations, including a method that includes receiving a block of information from non-processor memory at an interface between the non-processor memory and processor memory comprising two or more processor memory levels, determining whether the block of information received from the non-processor memory at the interface corresponds to encrypted instruction code, and decrypting the block of information at the interface between the non-processor memory and the processor memory for storage in one of the two or more levels of the processor memory in response to a determination that the received block of information corresponds to the encrypted instruction code. The block of information is stored at the one of the two or more levels of the processor memory without being decrypted when the received block of information is determined to correspond to data.

2. 发明授权

US09916449B2 Identification of backdoors and backdoor triggers 有权
公开(公告)号：US09916449B2
公开(公告)日：2018-03-13
申请号：US14773104
申请日：2013-11-12
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , Lakshminarasimhan Sethumadhavan , Adam Waksman , Matthew Suozzo
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman , Matthew Suozzo
IPC分类号： G06F21/56 , G06F21/71 , H04L29/06 , G06F11/263
CPC分类号： G06F21/566 , G06F11/263 , G06F21/56 , G06F21/71 , H04L63/1466
摘要： Disclosed are devices, systems, apparatus, methods, products, media, and other implementations, including a method that includes computing for one or more inputs of a circuit associated metrics representative of degree of influence that values of each of the one or more inputs have on at least one output dependent on the one or more inputs, and determining based, at least in part, on the computed metrics associated with the one or more inputs of a more inputs whether the at least one output dependent on the one or more inputs is part of a potentially malicious implementation.

3. 发明申请

US20130061322A1 Systems and Methods for Detecting Design-Level Attacks Against a Digital Circuit 有权
标题翻译：用于检测针对数字电路的设计级攻击的系统和方法
公开(公告)号：US20130061322A1
公开(公告)日：2013-03-07
申请号：US13580121
申请日：2011-02-28
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： G06F21/00
CPC分类号： G06F21/554 , G06F9/30145 , G06F9/3867 , G06F12/14 , G06F15/16 , G06F21/00 , G06F21/71 , G06F2221/2101
摘要： Systems and methods for detecting design-level attacks against a digital circuit which includes various functional units. A target unit is selected from among the functional units for monitoring and a predictor unit is arranged to receive events before they reach the target unit. A reactor unit is selected from among the functional units of the digital circuit which are arranged to receive events after they pass through the target unit. A monitor unit is arranged to receive predicted event messages from the predictor unit and actual event messages from the reactor unit. The monitor unit is configured to indicate an alarm based on a comparison of the predicted event messages received from the predictor unit and the actual event messages received from the reactor unit.
摘要翻译：用于检测包括各种功能单元的数字电路的设计级别攻击的系统和方法。从用于监视的功能单元中选择目标单元，并且预测单元布置成在到达目标单元之前接收事件。从数字电路的功能单元中选择反应器单元，其被布置成在它们通过目标单元之后接收事件。监视器单元布置成从预测器单元接收预测的事件消息和来自反应器单元的实际事件消息。监视器单元被配置为基于从预测器单元接收的预测事件消息与从反应器单元接收的实际事件消息的比较来指示警报。

4. 发明授权

US09325493B2 System and methods for silencing hardware backdoors 有权
公开(公告)号：US09325493B2
公开(公告)日：2016-04-26
申请号：US14671905
申请日：2015-03-27
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： H04L29/06 , G06F11/00 , G06F12/16 , G08B23/00 , H04L9/00 , G06F21/76
CPC分类号： H04L9/002 , G06F21/76 , H04L9/008 , H04L2209/16
摘要： Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.

5. 发明授权

US09037895B2 System and methods for silencing hardware backdoors 有权
标题翻译：用于消除硬件后门的系统和方法
公开(公告)号：US09037895B2
公开(公告)日：2015-05-19
申请号：US13273016
申请日：2011-10-13
申请人： Lakshminarasimhan Sethumadhavan , Adam Waksman
发明人： Lakshminarasimhan Sethumadhavan , Adam Waksman
IPC分类号： G06F1/04 , G06F21/76
CPC分类号： H04L9/002 , G06F21/76 , H04L9/008 , H04L2209/16
摘要： Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.
摘要翻译：用于防止安装在数字电路中的硬件后门的激活的方法，所述数字电路包括要被保护的一个或多个硬件单元。定时器在小于验证时期的周期内重复启动，并且硬件单元在计时器到期时复位，以防止启动基于时间的后门。被发送到硬件单元的数据在加密元素中被加密，以使它无法识别到存在于硬件单元中的单一作弊代码硬件后门。发送到硬件单元的指令被随机地或伪随机地重新排序，使用重新排序元素确定的顺序限制来呈现嵌入在硬件单元中存在的序列作弊码硬件后门的无法识别的指令中的激活指令序列。

6. 发明申请

US20090013135A1 UNORDERED LOAD/STORE QUEUE 有权
标题翻译：无节奏的载入/存储队列
公开(公告)号：US20090013135A1
公开(公告)日：2009-01-08
申请号：US12166491
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/312 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/383 , G06F9/3855
摘要： A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.
摘要翻译：一种方法和处理器，用于向具有无序执行的处理器的无序加载/存储队列提供满载/存储队列功能。加载和存储指令以执行顺序插入到加载/存储队列中。加载/存储队列中的每个条目包括与程序顺序相对应的标识。可以通过在第一CAM中搜索与要执行的加载或存储指令相同或重叠的所有地址来执行这种无序加载/存储队列中的冲突检测。可以在第二CAM中执行进一步的搜索以识别与要执行的加载或存储指令的序列号相关联的与较年或更旧的指令相关联的那些条目。地址CAM和Age CAM的输出结果在逻辑上为AND。

7. 发明授权

US10025929B2 Detection of anomalous program execution using hardware-based micro-architectural data 有权
公开(公告)号：US10025929B2
公开(公告)日：2018-07-17
申请号：US14778007
申请日：2013-11-05
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , Lakshminarasimhan Sethumadhavan , John Demme , Jared Schmitz , Adrian Tang , Sal Stolfo , Matthew Maycock
发明人： Lakshminarasimhan Sethumadhavan , John Demme , Jared Schmitz , Adrian Tang , Sal Stolfo , Matthew Maycock
IPC分类号： H04L9/00 , G06F21/56 , G06F21/57 , G06N99/00 , H04L9/32 , H04L29/06 , G06F11/34
摘要： Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes obtaining hardware-based micro-architectural data, including hardware-based micro-architectural counter data, for a hardware device executing one or more processes, and determining based, at least in part, on the hardware-based micro-architectural data whether at least one of the one or more processes executing on the hardware device corresponds to a malicious process. In some embodiments, determining based on the hardware-based micro-architectural data whether the at least one of the one or more processes corresponds to a malicious process may include applying one or more machine-learning procedures to the hardware-based micro-architectural data to determine whether the at least one of the one or more processes corresponds to the malicious process.

8. 发明申请

US20100325395A1 DEPENDENCE PREDICTION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的依赖性预测
公开(公告)号：US20100325395A1
公开(公告)日：2010-12-23
申请号：US12487804
申请日：2009-06-19
申请人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example.
摘要翻译：通常描述与存储器系统的依赖性预测相关的技术。各种实现可以包括存储对应于与至少一个加载操作相关联的至少一个预测类型的值的预测器存储器和具有多个状态的状态机。例如，状态机可以基于与每个状态相关联的预测类型以及相关联的预测类型的加载操作的相应先例来确定是否执行加载操作。状态机可以基于加载操作的结果进一步确定后续加载操作的预测类型。状态机的状态例如可以对应于预测类型，其可以是保守预测类型，积极预测类型或一个或多个N-存储预测类型。

9. 发明申请

US20090013160A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 有权
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：US20090013160A1
公开(公告)日：2009-01-08
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

10. 发明授权

US08855970B2 System and methods for precise microprocessor event counting 有权
标题翻译：精确微处理器事件计数的系统和方法
公开(公告)号：US08855970B2
公开(公告)日：2014-10-07
申请号：US13273035
申请日：2011-10-13
申请人： Lakshminarasimhan Sethumadhavan , John D. Demme
发明人： Lakshminarasimhan Sethumadhavan , John D. Demme
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/3024 , G06F11/3466 , G06F2201/815 , G06F2201/88
摘要： Method for providing precise microprocessor performance counter readings including detecting a swap back to a monitored process executing in a microprocessor. In response to the detected swap back to the monitored process, if the value read from the performance counter does not exceed the defined overflow threshold, the value of the performance counter stored in the first memory location is restored to the performance counter. If the value read from the performance counter exceeds the defined overflow threshold, the performance counter is set to zero and the value of the performance counter stored in the first memory location is used to increment an overflow memory location. If the value read from the performance counter exceeds the defined overflow threshold, at least one performance counter reading instruction is detected and in response to the detected at least one performance counter reading instruction, setting the counter output register to zero.
摘要翻译：用于提供精确的微处理器性能计数器读数的方法，包括检测到交换回到在微处理器中执行的监视过程。响应于检测到的交换回到监视的进程，如果从性能计数器读取的值不超过定义的溢出阈值，则存储在第一存储器位置的性能计数器的值被恢复到性能计数器。如果从性能计数器读取的值超过定义的溢出阈值，则性能计数器设置为零，并且使用存储在第一存储器位置的性能计数器的值来增加溢出存储器位置。如果从性能计数器读取的值超过定义的溢出阈值，则检测至少一个性能计数器读取指令，并且响应于检测到的至少一个性能计数器读取指令，将计数器输出寄存器设置为零。

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