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1. 发明申请

WO2006052262A2 INVERTED J-LEAD PACKAGE FOR POWER DEVICES 审中-公开
标题翻译：倒装J-LEAD封装的功率器件
公开(公告)号：WO2006052262A2
公开(公告)日：2006-05-18
申请号：PCT/US2004/041217
申请日：2004-12-09
申请人： LUO, Leeshawn , BHALLA, Anup , LUI, Sik , HO, Yueh-Se , CHANG, Mike , ZHANG, Xiao Tian
发明人： LUO, Leeshawn , BHALLA, Anup , LUI, Sik , HO, Yueh-Se , CHANG, Mike , ZHANG, Xiao Tian
IPC分类号： H01L23/28
CPC分类号： H01L24/48 , H01L23/49555 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/49 , H01L24/73 , H01L2224/05552 , H01L2224/05553 , H01L2224/05599 , H01L2224/0603 , H01L2224/32245 , H01L2224/371 , H01L2224/37599 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73265 , H01L2224/84801 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/0106 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.
摘要翻译：半导体封装包括具有多个引线和引线框垫的引线框架，引线框垫包括与其耦合的管芯，多个引线中的至少一个引线具有相对于封装的底表面向上倾斜的外部部分，将管芯连接到多个引线的金属连接器，以及封装管芯的树脂体，金属连接器和引线框架的至少一部分。

2. 发明申请

WO2006014690A3 POWER SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：WO2006014690A3
公开(公告)日：2006-02-09
申请号：PCT/US2005/025669
申请日：2005-07-20
申请人： ALPHA & OMEGA SEMICONDUCTOR LTD. , LUO, Leeshawn , BHALLA, Anup , LUI, Sik , ZHANG, Xiaotian , CHANG, Mike, F. , HO, Yueh-Se
发明人： LUO, Leeshawn , BHALLA, Anup , LUI, Sik , ZHANG, Xiaotian , CHANG, Mike, F. , HO, Yueh-Se
IPC分类号： H01L23/495
摘要： A semiconductor package (600) including a relatively thick lead frame (630) greater than the conventional 8mm to aid head dissipation having a plurality of leads and a first lead frame pad, the first lead frame pad (602) including a die coupled thereto, bonding wires (610) connecting the die to a plurality of leads, the bonding wires being aluminium and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame. Source lead is (616), drain lead (626), and gate lead is (612). (614) and (624) are locking holes. Source lead (616) may be a single lead to maximise the number of bonding wires to reduce on-resistance and inductance.

3. 发明申请

WO2005017994A1 INTEGRATED CIRCUIT PACKAGE FOR SEMICONDUCTOR DEVICES WITH IMPROVED ELECTRIC RESISTANCE AND INDUCTANCE 审中-公开
标题翻译：具有改善电阻和电感的半导体器件集成电路封装
公开(公告)号：WO2005017994A1
公开(公告)日：2005-02-24
申请号：PCT/US2003/022430
申请日：2003-07-14
申请人： ALPHA & OMEGA SEMICONDUCTOR, INC. , LUO, Leeshawn , BHALLA, Anup , HO, Yueh-Se , LIU, Sik, K. , CHANG, Mike
发明人： LUO, Leeshawn , BHALLA, Anup , HO, Yueh-Se , LIU, Sik, K. , CHANG, Mike
IPC分类号： H01L21/48
CPC分类号： H01L24/85 , H01L21/4821 , H01L23/49537 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/50 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05552 , H01L2224/05554 , H01L2224/05599 , H01L2224/05647 , H01L2224/0603 , H01L2224/45139 , H01L2224/48137 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49111 , H01L2224/49171 , H01L2224/49431 , H01L2224/85447 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/78 , H01L2224/45099 , H01L2924/00012 , H01L2924/01049
摘要： A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a "L" shape, a "C" shape, a "J" shape, an "I" shape or any combination thereof.
摘要翻译：一种半导体集成电路封装，具有引线框架（108），该引线框架（108）包括设置在管芯（100）下方的引线框架（103a）和设置在管芯的至少两个相邻侧面上的接合金属区域（101a）。接合金属区域（101a）的增加增加了金属区域（101a）和模具（100）之间的互连次数，以降低电阻和电感。此外，从封装的塑料体（106）辐射的外部端子的表面积如果没有最大化则增加，使得能够更快地消散热量并且降低外部端子电阻。该集成电路适用于MOSFET器件，并且用于源极端子（101）的接合金属区域（101a）。接合金属区域可以具有“L”形，“C”形，“J”形，“I”形或其任何组合。

4. 发明申请

WO2006050449A3 LOW COST POWER MOSFET WITH CURRENT MONITORING 审中-公开
公开(公告)号：WO2006050449A3
公开(公告)日：2006-05-11
申请号：PCT/US2005/039708
申请日：2005-11-02
申请人： ALPHA & OMEGA SEMICONDUCTOR LIMITED , LUI, Sik, K. , BHALLA, Anup
发明人： LUI, Sik, K. , BHALLA, Anup
IPC分类号： H01L23/495
摘要： A semiconductor integrated circuit package having a common source current sensing circuit includes a main die having a n integrated circuit, the main die including a source bonding pad and a gate bonding pad disposed on an upper surface, a leadframe having a leadframe pad disposed under the main die , and, a monitoring die including a source bonding pad and a gate bonding pad disposed on an upper surface, the monitoring die being coupled to the main die in such manner that the main die source bonding pad is coupled to the monitoring die source bonding pad and the main die gate bonding pad is coupled to the monitoring die gate bonding pad and such that the main die and monitoring die upper surfaces are adjacent to one another.

5. 发明申请

WO2007106422A2 SHIELDED GATE TRENCH(SGT) MOSFET CELLS IMPLEMENTED WITH A SCHOTTKY SOURCE CONTACT 审中-公开
标题翻译：屏蔽门（SGT）MOSFET电池实现与肖特基源联系
公开(公告)号：WO2007106422A2
公开(公告)日：2007-09-20
申请号：PCT/US2007/006165
申请日：2007-03-12
申请人： ALPHA & OMEGA SEMICONDUCTOR, LTD. , BHALLA, Anup , LUI, Sik, K.
发明人： BHALLA, Anup , LUI, Sik, K.
IPC分类号： H04J3/16
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one active cell further includes a trenched source contact opened between the trenches wherein the trenched source contact opened through a source region into a body region for electrically connecting the source region to a source metal disposed on top of an insulation layer wherein a trench bottom surface of the trenched source contact further covered with a conductive material to function as an integrated Schottky barrier diode in said active cell. A shielding structure is disposed at the bottom and insulated from the trenched gate to provide shielding effect for both the trenched gate and the Schottky diode.
摘要翻译：本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。至少一个有源电池还包括在沟槽之间开放的沟槽的源极触点，其中沟槽的源极触点通过源极区域开放到主体区域中，用于将源区域电连接到设置在绝缘层的顶部上的源极金属，其中沟槽底部沟槽源极接触表面进一步用导电材料覆盖，以用作所述活性电池中的集成肖特基势垒二极管。屏蔽结构设置在底部并与沟槽栅绝缘，以为沟槽栅极和肖特基二极管提供屏蔽效应。

6. 发明申请

WO2009088422A2 REDUCED MASK CONFIGURATION FOR POWER MOSFETS WITH ELECTROSTATIC DISCHARGE (ESD) CIRCUIT PROTECTION 审中-公开
标题翻译：具有静电放电（ESD）电路保护功率MOSFET的减少掩模配置
公开(公告)号：WO2009088422A2
公开(公告)日：2009-07-16
申请号：PCT/US2008/013638
申请日：2008-12-12
申请人： ALPHA & OMEGA SEMICONDUCTOR, LTD. , NG, Daniel , BHALLA, Anup
发明人： NG, Daniel , BHALLA, Anup , WANG, Xiaobin , WANG, Wei , SU, Yi
IPC分类号： H01L29/06 , H01L27/088
CPC分类号： H01L29/7811 , H01L27/0255 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/66734 , H01L29/7808 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.
摘要翻译：支撑在半导体衬底上的半导体功率器件包括设置在半导体衬底顶部的图案化ESD多晶硅层的第一部分上的静电放电（ESD）保护电路。所述半导体功率器件还包括构图的ESD多晶硅层的第二部分，其构成主体注入离子阻挡层，用于阻止注入体离子进入体内注入离子阻挡层下方的半导体衬底。在示例性实施例中，半导体衬底顶部上的静电放电（ESD）多晶硅层进一步覆盖半导体器件边缘上的划线，由此不再需要钝化层制造用于减少图案所需掩模的半导体器件钝化层。

7. 发明申请

WO2008070034A3 JUNCTION BARRIER SCHOTTKY (JBS) WITH FLOATING ISLANDS 审中-公开
公开(公告)号：WO2008070034A3
公开(公告)日：2008-06-12
申请号：PCT/US2007/024761
申请日：2007-12-01
申请人： ALPHA & OMEGA SEMICONDUCTOR, LTD. , PAN, Ji , BHALLA, Anup
发明人： PAN, Ji , BHALLA, Anup
IPC分类号： H01L31/111
摘要： A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

8. 发明申请

WO2008039548A2 TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY 审中-公开
标题翻译： TRENCH JUNCTION BARRIER控制的肖特
公开(公告)号：WO2008039548A2
公开(公告)日：2008-04-03
申请号：PCT/US2007/021107
申请日：2007-09-30
申请人： ALPHA & OMEGA SEMICONDUCTOR, LTD. , LUI, Sik, K.
发明人： LUI, Sik, K. , BHALLA, Anup
IPC分类号： H01L29/739 , H01L31/00
CPC分类号： H01L29/66727 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/66143 , H01L29/66734 , H01L29/7811 , H01L29/782 , H01L29/8725
摘要： A Schottky diode includes at least a trenched opened in a semiconductor substrate doped with a dopant of a first conductivity type wherein the trench is filled with a Schottky junction barrier metal. The Schottky diode further includes one or more dopant region of a second conductivity type surrounding sidewalk of the trench distributed along the depth of the trench for shielding a reverse leakage current through the sidewalk of the trench. The Schottky diode further includes a bottom-doped region of the second conductivity type surrounding a bottom surface of the trench and a top-doped region of the second conductivity type surrounding a top portion of the sidewalk of the trench. In a preferred embodiment, the first conductivity type k a N-type conductivity type and the middle-depth dopant region comprising a P-dopant region.
摘要翻译：肖特基二极管包括在掺杂有第一导电类型的掺杂剂的半导体衬底中开放的至少沟槽，其中沟槽填充有肖特基结阻挡金属。所述肖特基二极管进一步包括沿沟槽深度分布的围绕沟槽的第二导电类型的一个或多个掺杂区域，用于屏蔽通过沟槽的人行道的反向泄漏电流。肖特基二极管还包括围绕沟槽的底表面的第二导电类型的底部掺杂区域和围绕沟槽的人行道顶部的第二导电类型的顶部掺杂区域。在优选实施例中，第一导电类型k是N型导电类型，以及包含P掺杂区域的中间深度掺杂剂区域。

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