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1. 发明申请

WO2013078950A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013078950A1
公开(公告)日：2013-06-06
申请号：PCT/CN2012/084694
申请日：2012-11-15
申请人： LI, Yuan , GUO, Lei
发明人： LI, Yuan , GUO, Lei
IPC分类号： H01L27/00
CPC分类号： H01L33/0062 , H01L33/007 , H01L33/16 , H01L33/20
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (100); and a plurality of zigzag structures (200) formed on a surface of the substrate (100), in which each zigzag structure (200) has a first long side (202) and a first short side (204), the first long side (202) of one zigzag structure (200) is adjacent to the first short side (204) of another zigzag structure (200) adjacent to the one zigzag structure (200), each first long side (202) defines a first surface (300) of each zigzag structure (200), each first short side (204) defines a second surface (302) of each zigzag structure, and each first surface (300) is a growth surface for a compound semiconductor layer.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：衬底（100）; 以及形成在所述基板（100）的表面上的多个锯齿形结构（200），其中每个锯齿形结构（200）具有第一长边（202）和第一短边（204），所述第一长边一个之字形结构（200）的第一表面（202）与邻近一个之字形结构（200）的另一个锯齿形结构（200）的第一短边（204）相邻，每个第一长边（202）限定第一表面（300）每个Z字形结构（200）的每个第一短边（204）限定每个锯齿形结构的第二表面（302），并且每个第一表面（300）是化合物半导体层的生长表面。

2. 发明申请

WO2013078867A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013078867A1
公开(公告)日：2013-06-06
申请号：PCT/CN2012/078571
申请日：2012-07-12
申请人： LI, Yuan , GUO, Lei
发明人： LI, Yuan , GUO, Lei
IPC分类号： H01L33/16 , H01L33/02 , H01L33/00
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/0242 , H01L21/0243 , H01L21/02433 , H01L21/02609 , H01L21/02658 , H01L21/0275 , H01L29/04 , H01L29/0692 , H01L33/007 , H01L33/16 , H01L33/20 , H01L33/24 , H01L33/32
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (100); and a plurality of convex structures (200) formed on a surface of the substrate (100) and arranged in a longitudinal direction of the substrate (100), each convex structure (200) having a top surface (202), a bottom surface (204) located on the surface of the substrate, a first end surface (206) and a second end surface (208) parallel to each other, and a front side surface (210) and a rear side surface (212) parallel to each other, in which the rear side surface (212) of one of two adjacent convex structures (200) and the front side surface (210) of the other are located on a same plane to allow the plurality of convex structures (200) to form a zigzag structure.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：衬底（100）; 以及形成在所述基板（100）的表面上且沿着所述基板（100）的长度方向配置的多个凸部结构（200），每个凸起结构（200）具有顶面（202），底面 204），位于所述基板的表面上的第一端面（206）和彼此平行的第二端面（208）以及彼此平行的前侧表面（210）和后侧表面（212），其中两个相邻凸起结构（200）中的一个的后侧表面（212）和另一个的前侧表面（210）位于同一平面上，以允许所述多个凸起结构（200）形成曲折结构。

3. 发明申请

WO2013152707A1 CLOCK SIGNAL TRANSMISSION APPARATUS 审中-公开
标题翻译：时钟信号传输装置
公开(公告)号：WO2013152707A1
公开(公告)日：2013-10-17
申请号：PCT/CN2013/073921
申请日：2013-04-09
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L27/15
CPC分类号： G09G3/32 , G06F1/105 , H01L25/0753 , H01L33/60 , H01L2924/0002 , H04B10/803 , H01L2924/00
摘要： A clock signal transmission apparatus is provided. The clock signal transmission apparatus comprises: a modulator (4) for receiving a clock signal and modulating a light emitting device (2) according to the clock signal; the light emitting device (2) for emitting a light signal corresponding to the clock signal; and an integrated circuit chip (1) comprising: at least one light-to-electricity converter (11) for converting the light signal into an electric signal, and at least one demodulator (13) for demodulating the electric signal to obtain the clock signal.
摘要翻译：提供时钟信号发送装置。时钟信号传输装置包括：调制器（4），用于接收时钟信号并根据时钟信号调制发光器件（2）; 所述发光装置（2）用于发射对应于所述时钟信号的光信号; 以及集成电路芯片（1），包括：用于将所述光信号转换为电信号的至少一个光电转换器（11），以及用于解调所述电信号以获得所述时钟信号的至少一个解调器（13）。

4. 发明申请

WO2013117155A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013117155A1
公开(公告)日：2013-08-15
申请号：PCT/CN2013/071398
申请日：2013-02-05
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L21/20 , H01L33/00 , H01L29/02 , H01L21/02
CPC分类号： H01L29/1075 , H01L21/0237 , H01L21/02439 , H01L21/02521 , H01L21/02639 , H01L21/02647 , H01L29/2003
摘要： A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a porous structure in a region under the top surface of the substrate (100), thus forming a patterned structure on the porous structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.
摘要翻译：提供一种形成半导体结构的方法。该方法包括以下步骤：提供衬底（100）; 在所述基板（100）上形成第一单晶半导体层（200）; 蚀刻第一单晶半导体层（200）以形成延伸到衬底（100）的顶表面的多个孔或沟槽，或蚀刻第一单晶半导体层（200）和衬底（100）以形成多个孔或沟槽延伸到衬底（100）中; 通过所述多个孔或沟槽蚀刻所述衬底（100）以在所述衬底（100）的顶表面下方的区域中形成多孔结构，从而在所述多孔结构上形成图案化结构; 以及沉积单晶半导体材料以在所述图案化结构上形成第二单晶半导体层（300）。

5. 发明申请

WO2013117153A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013117153A1
公开(公告)日：2013-08-15
申请号：PCT/CN2013/071388
申请日：2013-02-05
申请人： GUO, Lei , LI, Yuan
发明人： GUO, Lei , LI, Yuan
IPC分类号： H01L21/02
CPC分类号： H01L29/1075 , H01L21/0237 , H01L21/02439 , H01L21/02521 , H01L21/02639 , H01L21/02647 , H01L21/0265 , H01L29/2003
摘要： A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a plurality of supporting structures (1001) in a region under the top surface of the substrate (100), thus forming a patterned structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.
摘要翻译：提供一种形成半导体结构的方法。该方法包括以下步骤：提供衬底（100）; 在所述基板（100）上形成第一单晶半导体层（200）; 蚀刻第一单晶半导体层（200）以形成延伸到衬底（100）的顶表面的多个孔或沟槽，或蚀刻第一单晶半导体层（200）和衬底（100），以形成多个孔或沟槽延伸到衬底（100）中; 通过所述多个孔或沟槽蚀刻所述衬底（100）以在所述衬底（100）的顶表面下方的区域中形成多个支撑结构（1001），从而形成图案化结构; 以及沉积单晶半导体材料以在所述图案化结构上形成第二单晶半导体层（300）。

6. 发明公开

EP3388512A1 METHOD FOR SEPARATING AND CULTURING MESENCHYMAL STEM CELLS FROM WHARTON'S JELLY TISSUE OF UMBILICAL CORD 有权
公开(公告)号：EP3388512A1
公开(公告)日：2018-10-17
申请号：EP15910085.8
申请日：2015-12-11
申请人： Guo, Lei , Li, Cheng
发明人： GUO, Lei
IPC分类号： C12N5/0775 , C12N5/0735
摘要： Provided is a method for separating and extracting mesenchymal stem cells from the human umbilical cord. The method uses healthy neonatal umbilical cord tissue; after cleaning and disinfection, mechanically pulverising same, separating the Wharton's jelly, and after treating with erythrocyte lysate, carrying out suspension culture in a serum-free culture medium. Replacing the liquid every 3-5 days; after the plate adherence rate reaches 30-70%, carrying out trypsin digestion, and then collecting the cells by centrifugation for passage amplification, until the rate of confluence of the cells reaches 80-90% confluence, thereby obtaining high purity umbilical cord mesenchymal stem cells.

7. 发明申请

WO2013159693A1 GROUP III-V SEMICONDUCTOR DC TRANSFORMER AND METHOD FOR FORMING SAME 审中-公开
标题翻译：第III-V族半导体直流变压器及其形成方法
公开(公告)号：WO2013159693A1
公开(公告)日：2013-10-31
申请号：PCT/CN2013/074556
申请日：2013-04-23
申请人： GUO, Lei , ZHAO, Dongjing
发明人： GUO, Lei , ZHAO, Dongjing
IPC分类号： H02M3/02 , H01L31/18
CPC分类号： H01L31/173 , H02M3/04 , Y02E10/56
摘要： A group III-V semiconductor DC transformer and a method for forming the same are provided. The group III-V semiconductor DC transformer comprises: an isolation layer (3) with a material of transparent insulating dielectric; a plurality of group III-V semiconductor light emitting diodes (1) formed on one surface of the isolation layer (3) for emitting a working light with specified wavelength to convert an electric energy into an optical energy; a plurality of group III-V semiconductor photovoltaic cells (2) formed on one surface of the isolation layer (3) for absorbing the working light to convert the optical energy into the electric energy, in which a working light spectrum of each group III-V semiconductor light emitting diode (1) is matched with that of each group III-V semiconductor photovoltaic cell (2), and the isolation layer (3) is transparent to the working light.
摘要翻译：提供III-V族半导体DC变压器及其形成方法。 III-V族半导体DC变压器包括：具有透明绝缘介电材料的隔离层（3）; 多个III-V族半导体发光二极管（1），形成在所述隔离层（3）的一个表面上，用于发射具有特定波长的工作光以将电能转换为光能; 形成在隔离层（3）的一个表面上的用于吸收工作光以将光能转换成电能的多个III-V族半导体光伏电池（2），其中每组III- V型半导体发光二极管（1）与各III-V族半导体光伏电池（2）的配合，隔离层（3）对于工作光是透明的。

8. 发明申请

WO2012163046A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2012163046A1
公开(公告)日：2012-12-06
申请号：PCT/CN2011/082109
申请日：2011-11-11
申请人： TSINGHUA UNIVERSITY , WANG, Jing , GUO, Lei
发明人： WANG, Jing , GUO, Lei
IPC分类号： H01L29/06 , H01L21/02 , H01L21/336
CPC分类号： H01L21/02378 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02494 , H01L21/02502 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L21/30608 , H01L21/3065 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a wafer (1100); a plurality of convex structures (1200) formed on the wafer (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50nm in width; and a first semiconductor film (1300) formed on the plurality of convex structures (1200), in which a part of the first semiconductor film (1300) is spaced apart from the wafer (1100).
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：晶片（1100）; 形成在所述晶片（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案以预定图案分隔并排列成阵列，并且每两个相邻凸起结构之间的空腔宽度小于50nm; 以及形成在所述多个凸起结构（1200）上的第一半导体膜（1300），其中所述第一半导体膜（1300）的一部分与所述晶片（1100）间隔开。

9. 发明申请

WO2012119418A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：WO2012119418A1
公开(公告)日：2012-09-13
申请号：PCT/CN2011/078946
申请日：2011-08-25
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/76283 , H01L21/76251 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300), a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region; and a plurality of shallow trench isolation structures (1900) extending into the silicon substrate (1100) and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在Ge层（1300）上的栅极堆叠（1600,1700），形成在栅极叠层（1600,1700）下方的沟道区域，以及形成在沟道区域侧面上的源极（1800）和漏极（1800） ; 以及多个浅沟槽隔离结构（1900），其延伸到硅衬底（1100）中并且填充有绝缘介电材料以在沟道区域中产生应变。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

10. 发明申请

WO2012119417A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：WO2012119417A1
公开(公告)日：2012-09-13
申请号：PCT/CN2011/078944
申请日：2011-08-25
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L29/06 , H01L29/78 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76283 , H01L21/76251 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300), a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region; and a Si N stress cap layer (1900) covering the gate stack (1600, 1700) to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在Ge层（1300）上的栅极堆叠（1600,1700），形成在栅极叠层（1600,1700）下方的沟道区域，以及形成在沟道区域侧面上的源极（1800）和漏极（1800） ; 以及覆盖栅极堆叠（1600,1700）的Si N应力覆盖层（1900），以在沟道区域中产生应变。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

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