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1. 发明申请

WO2012119418A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：WO2012119418A1
公开(公告)日：2012-09-13
申请号：PCT/CN2011/078946
申请日：2011-08-25
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/76283 , H01L21/76251 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300), a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region; and a plurality of shallow trench isolation structures (1900) extending into the silicon substrate (1100) and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在Ge层（1300）上的栅极堆叠（1600,1700），形成在栅极叠层（1600,1700）下方的沟道区域，以及形成在沟道区域侧面上的源极（1800）和漏极（1800） ; 以及多个浅沟槽隔离结构（1900），其延伸到硅衬底（1100）中并且填充有绝缘介电材料以在沟道区域中产生应变。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

2. 发明申请

WO2012119417A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：WO2012119417A1
公开(公告)日：2012-09-13
申请号：PCT/CN2011/078944
申请日：2011-08-25
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L29/06 , H01L29/78 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76283 , H01L21/76251 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300), a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region; and a Si N stress cap layer (1900) covering the gate stack (1600, 1700) to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在Ge层（1300）上的栅极堆叠（1600,1700），形成在栅极叠层（1600,1700）下方的沟道区域，以及形成在沟道区域侧面上的源极（1800）和漏极（1800） ; 以及覆盖栅极堆叠（1600,1700）的Si N应力覆盖层（1900），以在沟道区域中产生应变。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

3. 发明申请

WO2012119419A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：WO2012119419A1
公开(公告)日：2012-09-13
申请号：PCT/CN2011/078948
申请日：2011-08-25
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/76283 , H01L21/76251 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate (1100), in which an oxide insulating layer (1200) is formed on a surface of the silicon substrate (1100); a Ge layer (1300) formed on the oxide insulating layer (1200), in which a first passivation layer (1400) is formed between the Ge layer (1300) and the oxide insulating layer (1200); a gate stack (1600, 1700) formed on the Ge layer (1300); and a channel region formed below the gate stack (1600, 1700), and a source (1800) and a drain (1800) formed on sides of the channel region, in which the source (1800) and the drain (1800) are a Si x Ge -x :C source and a Si x Ge -x :C drain respectively to produce a tensile 10 strain in the channel region, in which x is within a range from 0 to 1 and a content of C is within a range from 0 to 7.5%. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：在硅衬底（1100）的表面上形成氧化物绝缘层（1200）的硅衬底（1100）; 形成在氧化物绝缘层（1200）上的Ge层（1300），其中在Ge层（1300）和氧化物绝缘层（1200）之间形成第一钝化层（1400）; 形成在所述Ge层（1300）上的栅叠层（1600,1700）; 以及形成在所述栅极堆叠（1600,1700）下面的沟道区域，以及形成在所述沟道区域的侧面上的源极（1800）和漏极（1800），所述源极（1800）和所述漏极（1800） Si x Ge-X：C源和Si x Ge-X：C漏极，以在沟道区域中产生拉伸10应变，其中x在0至1的范围内，并且C的含量在范围内从0％到7.5％。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

4. 发明申请

WO2012041087A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：WO2012041087A1
公开(公告)日：2012-04-05
申请号：PCT/CN2011/076392
申请日：2011-06-27
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L29/06 , H01L21/02 , H01L29/12 , H01L21/20
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for forming the same are provided. The semiconductor device comprises: a substrate (1); an insulating layer (2), formed on the substrate (1) and having a trench (21) to expose an upper surface of the substrate (1); a first buffer layer (3), formed on the substrate (1) and in the trench (21); and a compound semiconductor layer (4), formed on the first buffer layer (3), wherein an aspect ratio of the trench (21) is larger than 1 and smaller than 10, wherein the first buffer layer (3) is formed by a low-temperature reduced pressure chemical vapor deposition process at a temperature between 200°C and 500°C, and wherein the compound semiconductor layer (4) is formed by a low-temperature metal organic chemical vapor deposition process at a temperature between 200°C and 600°C.
摘要翻译：提供半导体器件及其形成方法。半导体器件包括：衬底（1）; 形成在所述基板（1）上并具有用于露出所述基板（1）的上表面的沟槽（21）的绝缘层（2）; 形成在所述基板（1）和所述沟槽（21）中的第一缓冲层（3）; 和形成在第一缓冲层（3）上的化合物半导体层（4），其中沟槽（21）的纵横比大于1且小于10，其中第一缓冲层（3）由在200℃〜500℃的温度下进行低温减压化学气相沉积工艺，其中化合物半导体层（4）通过低温金属有机化学气相沉积工艺在200℃ 和600℃。

5. 发明申请

WO2012100519A1 GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：导通绝缘体结构及其形成方法
公开(公告)号：WO2012100519A1
公开(公告)日：2012-08-02
申请号：PCT/CN2011/077703
申请日：2011-07-27
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L29/78684 , H01L21/76256 , H01L29/4908 , H01L29/7842 , H01L29/78603 , H01L29/78609
摘要： A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.
摘要翻译：提供一种形成绝缘体上Ge结构的方法，包括以下步骤：在衬底（2000）上形成Ge层（1200）; 处理所述Ge层（1200）的第一表面以形成第一半导体金属 - 锗化物钝化层（1300）; 将第一半导体金属 - 锗化物钝化层（1300）与硅衬底（1100）接合，其中在所述硅衬底（1100）的表面上形成氧化物绝缘层; 并移除基板（2000）。此外，还提供了通过该方法形成的绝缘体上Ge结构。

6. 发明申请

WO2011147256A1 LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：低肖特基二极管半导体结构及其形成方法
公开(公告)号：WO2011147256A1
公开(公告)日：2011-12-01
申请号：PCT/CN2011/073904
申请日：2011-05-10
申请人： TSINGHUA UNIVERSITY , WANG, Jing , WANG, Wei , GUO, Lei , XU, Jun
发明人： WANG, Jing , WANG, Wei , GUO, Lei , XU, Jun
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/0895 , H01L29/1054 , H01L29/41783 , H01L29/517 , H01L29/66477 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： A low Schottky barrier semiconductor structure is provided. The structure comprises: a substrate (100); a SiGe layer with low Ge content formed on the substrate; a channel layer (900) with high Ge content formed on the SiGe layer; a gate stack (200) formed on the substrate and a sidewall (400) of one or more layers formed on both sides of the gate stack; metal source/drain (300) formed in the channel layer and on the both sides of the gate stack, respectively; and an insulation layer (600) formed between the substrate and the metal source and between the substrate and the metal drain, respectively. A method for forming the low Schottky barrier semiconductor structure is also provided.
摘要翻译：提供了一种低肖特基势垒半导体结构。该结构包括：基底（100）; 在基板上形成具有低Ge含量的SiGe层; 在SiGe层上形成具有高Ge含量的沟道层（900）; 形成在所述基板上的栅极堆叠（200）和形成在所述栅极堆叠的两侧上的一个或多个层的侧壁（400）金属源极/漏极（300）分别形成在沟道层和栅极堆叠的两侧; 以及形成在所述基板和所述金属源之间以及所述基板和所述金属排出口之间的绝缘层（600）。还提供了形成低肖特基势垒半导体结构的方法。

7. 发明申请

WO2012129894A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2012129894A1
公开(公告)日：2012-10-04
申请号：PCT/CN2011/079442
申请日：2011-09-07
申请人： TSINGHUA UNIVERSITY , WANG, Jing , XU, Jun , GUO, Lei
发明人： WANG, Jing , XU, Jun , GUO, Lei
IPC分类号： H01L21/20 , H01L29/161
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02658 , H01L29/1054
摘要： A semiconductor structure is provided, comprising: a Si substrate (1100); a porous structure layer (1200) formed on the Si substrate (1100), in which the porous structure layer (1200) has a flat surface and comprises a Si 1-x Ge x layer with low Ge content; and a Ge-containing layer (1300) formed on the porous structure layer (1200), in which the Ge-containing layer (1300) comprises a Ge layer or a Si 1-y Ge y layer with high Ge content and x≤y. Further, a method for forming the semiconductor structure is also provided.
摘要翻译：提供一种半导体结构，包括：Si衬底（1100）; 形成在所述Si衬底（1100）上的多孔结构层（1200），其中所述多孔结构层（1200）具有平坦表面并且包括具有低Ge含量的Si 1-x Ge x层; 和形成在所述多孔结构层（1200）上的含Ge层，其中所述含Ge层包括Ge层或具有高Ge含量且x = y的Si1-yGey层。此外，还提供了一种用于形成半导体结构的方法。

8. 发明申请

WO2013177855A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2013177855A1
公开(公告)日：2013-12-05
申请号：PCT/CN2012/078789
申请日：2012-07-18
申请人： TSINGHUA UNIVERSITY , WANG, Wei , WANG, Jing , GUO, Lei
发明人： WANG, Wei , WANG, Jing , GUO, Lei
IPC分类号： H01L29/04 , H01L21/335
CPC分类号： H01L29/7849 , H01L29/78603 , H01L29/78654 , H01L29/78681 , H01L29/78684
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate (100); a rare earth oxide layer (200) formed on the semiconductor substrate (100); a channel region (300) formed on the rare earth oxide layer (200); and a source region (400) and a drain region (500) formed at both sides of the channel region (300) respectively, in which a relationship between a lattice constant a of the rare earth oxide layer (200) and a lattice constant b of a semiconductor material of the channel region (300) and/or the source region (400) and the drain region (500) is a = (n ± c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：半导体衬底（100）; 形成在半导体衬底（100）上的稀土氧化物层（200）; 形成在所述稀土氧化物层（200）上的沟道区（300）。以及分别形成在沟道区（300）的两侧的源区（400）和漏区（500），其中稀土氧化物层（200）的晶格常数a与晶格常数b 沟道区域（300）和/或源极区域（400）和漏极区域（500）的半导体材料是a =（n±c）b，其中n是整数，c是晶格的失配比常数，0

9. 发明申请

WO2012163047A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2012163047A1
公开(公告)日：2012-12-06
申请号：PCT/CN2011/082110
申请日：2011-11-11
申请人： TSINGHUA UNIVERSITY , WANG, Jing , GUO, Lei
发明人： WANG, Jing , GUO, Lei
IPC分类号： H01L29/06 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823481
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (1100); a plurality of convex structures (1200) formed on the substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity; a plurality of floated films (1300), in which each floated film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200), the floated films (1300) are partitioned into a plurality of sets, a channel layer is formed on a convex structure (1200) between the floated films (1300) in each set, a source region and a drain region are formed on two sides of the channel layer respectively, and an isolation portion (1200) is set between two adjacent sets of floated films (1300); and a gate stack (1400) formed on each channel layer.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：衬底（1100）; 形成在所述基板（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）由空腔分隔开; 多个浮动膜（1300），其中每个浮动膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接，浮动膜（1300）被划分为多组，在每组中的浮动膜（1300）之间的凸形结构（1200）上形成沟道层，在沟道层的两侧分别形成源极区和漏极区，以及隔离部分（1200）设置在两组相邻的漂浮膜（1300）之间; 和形成在每个沟道层上的栅叠层（1400）。

10. 发明申请

WO2012163046A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：WO2012163046A1
公开(公告)日：2012-12-06
申请号：PCT/CN2011/082109
申请日：2011-11-11
申请人： TSINGHUA UNIVERSITY , WANG, Jing , GUO, Lei
发明人： WANG, Jing , GUO, Lei
IPC分类号： H01L29/06 , H01L21/02 , H01L21/336
CPC分类号： H01L21/02378 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02494 , H01L21/02502 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/0265 , H01L21/30608 , H01L21/3065 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a wafer (1100); a plurality of convex structures (1200) formed on the wafer (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern and arranged in an array, and the cavity between every two adjacent convex structures is less than 50nm in width; and a first semiconductor film (1300) formed on the plurality of convex structures (1200), in which a part of the first semiconductor film (1300) is spaced apart from the wafer (1100).
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：晶片（1100）; 形成在所述晶片（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案以预定图案分隔并排列成阵列，并且每两个相邻凸起结构之间的空腔宽度小于50nm; 以及形成在所述多个凸起结构（1200）上的第一半导体膜（1300），其中所述第一半导体膜（1300）的一部分与所述晶片（1100）间隔开。

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