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1. 发明授权

US08627174B2 Memory devices and systems including error-correction coding and methods for error-correction coding 有权
标题翻译：存储器件和系统包括纠错编码和纠错编码方法
公开(公告)号：US08627174B2
公开(公告)日：2014-01-07
申请号：US12132754
申请日：2008-06-04
申请人： Kyung-hyun Kim , Kwang-il Park , In-chul Jeong
发明人： Kyung-hyun Kim , Kwang-il Park , In-chul Jeong
IPC分类号： G11C29/00
CPC分类号： H04L1/0042
摘要： In one aspect, a memory device includes a memory cell array, parallel internal data paths which transmit internal data to and from the memory cell array, a data driver which transmits and receives external data, and a data buffer which delays and transfers the external data received by the data driver to the internal data paths, and which delays and transfers the internal data transmitted from the memory cell array to the data driver. The memory device further includes an error correction code generator which generates an error correction code (EC) based on the internal data transmitted on the internal data paths, an EC buffer which delays the error correction code generated by the error correction code generator, an EC driver which transmits the error correction codes delayed by the EC buffer, and a latency controller which variably controls a delay time of at least one of the data buffer and the EC buffer.
摘要翻译：一方面，存储器件包括存储单元阵列，将内部数据传送到存储单元阵列和从存储单元阵列发送内部数据的并行内部数据路径，发送和接收外部数据的数据驱动器以及延迟和传送外部数据的数据缓冲器由数据驱动器接收到内部数据路径，并且延迟并将从存储单元阵列发送的内部数据传送到数据驱动器。存储装置还包括纠错码发生器，该纠错码产生器基于在内部数据路径上发送的内部数据产生纠错码（EC），延迟由纠错码发生器产生的纠错码的EC缓冲器，EC 发送由EC缓冲器延迟的纠错码的驱动器，以及可变地控制数据缓冲器和EC缓冲器中的至少一个的延迟时间的等待时间控制器。

2. 发明授权

US07814239B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
标题翻译：实现时钟镜像方案和相关内存系统的内存设备和时钟镜像方法
公开(公告)号：US07814239B2
公开(公告)日：2010-10-12
申请号：US12045289
申请日：2008-03-10
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

3. 发明授权

US07772907B2 Linear digital phase interpolator and semi-digital delay locked loop (DLL) 有权
标题翻译：线性数字相位插值器和半数字延迟锁定环（DLL）
公开(公告)号：US07772907B2
公开(公告)日：2010-08-10
申请号：US12255170
申请日：2008-10-21
申请人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
发明人： Jin-gook Kim , Seung-jun Bae , Kwang-il Park
IPC分类号： H03H3/00 , H03K5/13
CPC分类号： H03L7/0814 , H03L7/07
摘要： Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state. The phase indicating signal indicates a lead/lag phase relationship between the first and second input signals and is generated in a controller of a circuit of the semi-digital DLL.
摘要翻译：提供了一种数字相位内插器，其执行与两个输入信号的输入顺序无关的线性相位插值和包括并控制相同的半数字延迟锁定环（DLL）。相位插值器包括：由相位指示信号控制的第一时钟反相器，并通过反相第一输入信号向公共输出端提供第一输出信号;以及由相位指示信号控制的第二时钟反相器，并提供第二输出信号通过反转第二输入信号到公共输出端子。当相位指示信号处于第一逻辑状态时，第二时钟反相器由第一输入信号计时，当相位指示信号处于第二逻辑状态时，第一时钟反相器由第二输入信号计时。相位指示信号表示第一和第二输入信号之间的引导/滞后相位关系，并且在半数字DLL的电路的控制器中产生。

4. 发明申请

US20100045491A1 INPUT/OUTPUT (IO) INTERFACE AND METHOD OF TRANSMITTING IO DATA 失效
标题翻译：输入/输出（IO）接口和传输IO数据的方法
公开(公告)号：US20100045491A1
公开(公告)日：2010-02-25
申请号：US12547204
申请日：2009-08-25
申请人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
发明人： Seung-jun Bae , Young-hyun Jun , Joo-sun Choi , Kwang-il Park , Sang-hyup Kwak
IPC分类号： H03M7/00
CPC分类号： H03M5/06 , G11C7/1006
摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.
摘要翻译：输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个的交流耦合方法中的编码数据。数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

5. 发明申请

US20090268528A1 Semiconductor memory device and access method thereof 有权
标题翻译：半导体存储器件及其访问方法
公开(公告)号：US20090268528A1
公开(公告)日：2009-10-29
申请号：US12385121
申请日：2009-03-31
申请人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
发明人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/18 , G11C7/08 , G11C8/12 , G11C11/4076 , G11C11/4091
摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.
摘要翻译：示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

6. 发明申请

US20070109030A1 Phase-Locked Loop Integrated Circuits Having Fast Phase Locking Characteristics 审中-公开
标题翻译：具有快速锁相特性的锁相环集成电路
公开(公告)号：US20070109030A1
公开(公告)日：2007-05-17
申请号：US11623437
申请日：2007-01-16
申请人： Kwang-il Park
发明人： Kwang-il Park
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/093 , H03L7/10 , H03L7/18 , Y10S331/02
摘要： A phase-locked loop (PLL) integrated circuit includes a voltage-controlled oscillator and a loop filter having first and second input terminals and an output terminal coupled to an input of the voltage-controlled oscillator. A charge pump and a phase-lock accelerator are provided. The charge pump is configured to drive the first input terminal of the loop filter with a pump output signal and the phase-lock accelerator is configured to drive the second input terminal of the loop filter with an analog output signal. The phase-lock accelerator is responsive to a reference clock signal and a feedback clock signal.
摘要翻译：锁相环（PLL）集成电路包括压控振荡器和具有第一和第二输入端的环路滤波器和耦合到压控振荡器的输入的输出端。提供电荷泵和锁相加速器。电荷泵被配置为用泵输出信号驱动环路滤波器的第一输入端，并且锁相加速器被配置为用模拟输出信号驱动环路滤波器的第二输入端。相位锁定加速器响应于参考时钟信号和反馈时钟信号。

7. 发明授权

US08422333B2 Semiconductor memory device and access method thereof 有权
公开(公告)号：US08422333B2
公开(公告)日：2013-04-16
申请号：US13360093
申请日：2012-01-27
申请人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
发明人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C8/18 , G11C7/08 , G11C8/12 , G11C11/4076 , G11C11/4091
摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.

8. 发明授权

US08180939B2 Memory devices implementing clock mirroring scheme and related memory systems and clock mirroring methods 有权
公开(公告)号：US08180939B2
公开(公告)日：2012-05-15
申请号：US13013157
申请日：2011-01-25
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F13/12
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

9. 发明授权

US08125847B2 Semiconductor memory device and access method thereof 有权
标题翻译：半导体存储器件及其访问方法
公开(公告)号：US08125847B2
公开(公告)日：2012-02-28
申请号：US12385121
申请日：2009-03-31
申请人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
发明人： Dae-Hyun Kim , Kwang-il Park , Kyoung-Ho Kim , Hyun-Jin Kim , Hye-Ran Kim
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C8/18 , G11C7/08 , G11C8/12 , G11C11/4076 , G11C11/4091
摘要： Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.
摘要翻译：示例性实施例提供半导体存储器件，其可以包括：布置成多行和列的单元阵列; 以及响应于写入和读取对应于在周期可变的访问时间的访问时间，对单元阵列执行写入和读取操作的读出放大器。读出放大器根据访问时间的周期来调整写入和读出数据的脉冲宽度。

10. 发明申请

US20110029697A1 MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
标题翻译：存储器件实现时钟模式和相关的存储器系统和时钟模式
公开(公告)号：US20110029697A1
公开(公告)日：2011-02-03
申请号：US12902328
申请日：2010-10-12
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F3/00
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.
摘要翻译：存储器件被配置为在第一和第二数据输入/输出模式下操作。存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。时钟信号线被配置为将时钟传送到存储器件内部的集成电路。第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

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