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1. 发明授权

US06873004B1 Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof 有权
标题翻译：虚拟接地单晶体管存储单元，并入其的存储器阵列及其操作方法
公开(公告)号：US06873004B1
公开(公告)日：2005-03-29
申请号：US10358645
申请日：2003-02-04
申请人： Kyung Joon Han , Steve K. Hsia , Joo Weon Park , Gyu-Wan Kwon , Jong Seuk Lee
发明人： Kyung Joon Han , Steve K. Hsia , Joo Weon Park , Gyu-Wan Kwon , Jong Seuk Lee
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/66825 , H01L29/7885
摘要： An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.
摘要翻译：不对称的虚拟接地单晶体管浮动栅极存储单元具有覆盖p阱中的沟道区的浮置栅极，位于重掺杂n +漏极区和轻掺杂n-源区之间的沟道区。称为“卤素”的重掺杂p +区被设置在与重掺杂n +漏极相邻的沟道中。浮栅通过通常薄的隧道氧化物与沟道区间隔开。具有渐变源/沟道结的轻掺杂源减少源侧CHE生成。在一个变型中，源极和浮置栅极之间的较厚的氧化物减少了源极侧的CHE注入。在与漏极相邻的沟道中具有卤素注入的重掺杂漏极增强漏侧CHE生成。

2. 发明授权

US06728140B2 Threshold voltage convergence 有权
标题翻译：门限电压收敛
公开(公告)号：US06728140B2
公开(公告)日：2004-04-27
申请号：US10011157
申请日：2001-12-05
申请人： Kyung Joon Han , Joo Weon Park , Gyu-Wan Kwon , Dung Tran , Steve K. Hsia , Jong Seuk Lee , Dae Hyun Kim
发明人： Kyung Joon Han , Joo Weon Park , Gyu-Wan Kwon , Dung Tran , Steve K. Hsia , Jong Seuk Lee , Dae Hyun Kim
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/3404
摘要： A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.
摘要翻译：收敛信号包括用于在一个或多个快闪EEPROM存储单元（晶体管）中执行收敛过程的一系列电压脉冲。在一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更高的电压。在另一种情况下，会聚信号中的后续电压脉冲各自具有比先前脉冲更长的持续时间。集成电路包括存储单元的阵列和控制将收敛信号应用于一个或多个存储器单元的擦除控制单元。集成电路可以是使用批量，扇区或页面模式擦除的串行或并行闪存EEPROM。

3. 发明授权

US06826080B2 Virtual ground nonvolatile semiconductor memory array architecture and integrated circuit structure therefor 有权
标题翻译：虚拟地非易失性半导体存储器阵列结构及其集成电路结构
公开(公告)号：US06826080B2
公开(公告)日：2004-11-30
申请号：US10154979
申请日：2002-05-24
申请人： Joo Weon Park , Kyung Joon Han , Gyu-Wan Kwon , Jong Seuk Lee
发明人： Joo Weon Park , Kyung Joon Han , Gyu-Wan Kwon , Jong Seuk Lee
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/08
摘要： In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.
摘要翻译：在非易失性存储单元阵列中，每个扇区的存储单元被组织成连续单元组，这些组优选地具有相同的尺寸，并且优选地通过适当的隔离结构（例如场电介质）在行和列方向上彼此隔离或沟槽电介质。由于单元组隔离，每组列线可以通过其自己的相对较小的程序列选择进行解码，优选地以所有列列组为基本相同的形式复制。虽然每个节目列选择优选地用于解码一组列线，但是如果需要解码两组或更多组列线，则可以使用较大的节目列选择。读列选择可以根据需要对一行或多组列线进行解码。解码的列线的数量可以与解码的列线的数量相同或不同。

4. 发明授权

US07558900B2 Serial flash semiconductor memory 有权
标题翻译：串行闪存半导体存储器
公开(公告)号：US07558900B2
公开(公告)日：2009-07-07
申请号：US11078205
申请日：2005-03-11
申请人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
发明人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
IPC分类号： G06F13/14 , G06F3/00 , G06F13/42
CPC分类号： G11C7/1045 , G11C8/04 , G11C16/26 , G11C2207/108 , G11C2216/30
摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.
摘要翻译：串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。在单位串行模式下，数据传输通过引脚逐位传输。在多位串行模式下，通过各个引脚一次传输多个连续位。串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装。单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率显着快于标准串行闪存的可用性。

5. 发明申请

US20100049948A1 Serial flash semiconductor memory 审中-公开
标题翻译：串行闪存半导体存储器
公开(公告)号：US20100049948A1
公开(公告)日：2010-02-25
申请号：US12459590
申请日：2009-07-02
申请人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
发明人： Robin J. Jigour , Eungjoon Park , Joo Weon Park , Jong Seuk Lee
IPC分类号： G06F9/30 , G06F12/00 , G06F12/02
CPC分类号： G11C7/1045 , G11C8/04 , G11C16/26 , G11C2207/108 , G11C2216/30
摘要： A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.
摘要翻译：串行闪存具有多个可配置引脚，其中至少一个可选择性地配置用于单位串行数据传输或多位串行数据传输。在单位串行模式下，数据传输通过引脚逐位传输。在多位串行模式下，通过各个引脚一次传输多个连续位。串行闪存可能具有16个或更少的引脚，甚至8个或更少的引脚，因此可以使用低引脚数封装，例如8引脚或16引脚SOIC封装和8接点MLP / QFN / SON封装。单位串行类型协议的可用性支持与许多现有系统的兼容性，而多位串行类型协议的可用性使得串行闪存能够在可以支持它们的系统中提供数据传输速率显着快于标准串行闪存的可用性。

6. 发明授权

US5689464A Column repair circuit for integrated circuits 失效
标题翻译：集成电路列修复电路
公开(公告)号：US5689464A
公开(公告)日：1997-11-18
申请号：US600599
申请日：1994-04-19
申请人： Jong Seuk Lee , Seung Min Kim , Jae Hyeoung Kim , Sang Ho Lee
发明人： Jong Seuk Lee , Seung Min Kim , Jae Hyeoung Kim , Sang Ho Lee
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/812 , G11C29/846
摘要： A column repair circuit for a semiconductor memory having an input/output selection circuit for inputting a control signal, selecting a bit line and a bit bar line corresponding to a faulty memory cell and replacing the selected bit line and bit bar line with a spare bit line and a spare bit bar line. The input/output selection circuit includes an input stage for inputting the control signal, a spare bit line and a spare bit bar line, and a plurality of fuses each having one side connected to the input stage and other side connected to a plurality of resistors. The other side of the resistors are connected to ground for outputting the output signals. The input/output selection circuit further has a plurality of n-channel MOSFETs each including a gate connected to each of the other stages of the plurality of fuses via the resistors in a 2 to 1 manner for inputting the output signals. The drains of the MOSFETS are connected to the spare bit line and spare bit bar line and their sources are connected to each of the plurality of data bit lines and the plurality of data bit bar lines for functioning as a switch. Therefore, the present invention can provide the column repair circuit for a semiconductor memory which is capable of increasing its repair yield by adding the input/output selecting circuit enabling input/output selecting.
摘要翻译：一种用于半导体存储器的列修复电路，具有用于输入控制信号的输入/输出选择电路，选择与故障存储器单元相对应的位线和位线，并用备用位替换所选位线和位线线和备用位线。输入/输出选择电路包括用于输入控制信号的输入级，备用位线和备用位线条，以及多个熔丝，每个熔丝具有连接到输入级的一侧和连接到多个电阻器的另一侧。电阻的另一侧连接到地，用于输出输出信号。所述输入/输出选择电路还具有多个n沟道MOSFET，每个n沟道MOSFET包括通过所述电阻器以多个熔丝连接到所述多个熔丝中的每一个的栅极，以2:1的方式输入所述输出信号。 MOSFETS的漏极连接到备用位线和备用位线，并且它们的源极连接到用作开关的多个数据位线和多个数据位线中的每一个。因此，本发明可以提供半导体存储器的列修复电路，该半导体存储器能够通过添加能够进行输入/输出选择的输入/输出选择电路来提高其修复产率。

7. 发明授权

US5920884A Nonvolatile memory interface protocol which selects a memory device, transmits an address, deselects the device, subsequently reselects the device and accesses data 失效
标题翻译：非易失性存储器接口协议，其选择存储器件，发送地址，取消选择器件，随后重新选择器件并访问数据
公开(公告)号：US5920884A
公开(公告)日：1999-07-06
申请号：US873979
申请日：1997-06-12
申请人： Earle Willis Jennings, III , Jong Seuk Lee
发明人： Earle Willis Jennings, III , Jong Seuk Lee
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/4239 , Y02B60/1228 , Y02B60/1235
摘要： A non-volatile memory access protocol that facilitates concurrent accessing operations to multiple non-volatile memory components. This approach provides significant speed advantages over prior art non-volatile protocols. Also, power consumption is reduced in comparison to prior art synchronous protocols used for volatile memory because each memory component need not be continuously selected.
摘要翻译：一种促进对多个非易失性存储器组件的并发访问操作的非易失性存储器访问协议。这种方法比现有技术的非易失性协议提供了显着的速度优势。此外，与用于易失性存储器的现有技术的同步协议相比，功耗被降低，因为不需要连续选择每个存储器组件。

8. 发明授权

US06279070B1 Multistep pulse generation circuit and method of erasing a flash memory cell using the same 有权
标题翻译：多步骤脉冲发生电路及使用其擦除闪存单元的方法
公开(公告)号：US06279070B1
公开(公告)日：2001-08-21
申请号：US09330131
申请日：1999-06-11
申请人： Jae Heon Jeong , Jong Seuk Lee
发明人： Jae Heon Jeong , Jong Seuk Lee
IPC分类号： G06F1200
CPC分类号： G11C16/16 , G11C16/32 , G11C2216/20
摘要： There is disclosed a multi-step pulse generating circuit and a method of erasing a flash memory cell using the same, which can shorten the erase time for the flash memory and reduce the size of a device, in a way that it stores the information at the time when the suspense command is input during the multi-step pulse erase operation, switches it into a read mode, and resumes the erase operation from the time when the information is stored.
摘要翻译：公开了一种多级脉冲发生电路和使用该闪存存储单元擦除闪存单元的方法，其可以缩短闪存的擦除时间并减小设备的尺寸，方式是将其存储在在多步脉冲擦除操作期间输入挂起指令的时间，将其切换到读取模式，并从信息存储时恢复擦除操作。

9. 发明授权

US6084798A Non-volatile memory structure 有权
标题翻译：非易失性存储器结构
公开(公告)号：US6084798A
公开(公告)日：2000-07-04
申请号：US345086
申请日：1999-06-30
申请人： Jong Seuk Lee
发明人： Jong Seuk Lee
IPC分类号： G11C16/04 , G11C16/08 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11519 , G11C16/0416 , G11C16/08
摘要： The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled. A sector of the nonvolatile Flash EEPROM array preferably comprises 8 rows and 512 columns of transistors and a block preferably comprises 128 vertically stacked sectors.
摘要翻译：本发明提供了一种新颖的非易失性闪存EEPROM阵列设计，其允许阵列，块或扇区擦除功能。本发明的相对简单的晶体管设计布局允许擦除EEPROM阵列的小部分而不影响存储在阵列的剩余部分中的数据。另外，考虑到闪存EEPROM阵列的块结构布局，阵列中的相邻块可以共享晶体管控制电路，从而使阵列的尺寸最小化。新颖的非易失性闪存EEPROM阵列优选地包括多个块，其包括多个NOR栅极晶体管的扇区。每个晶体管都有漏极，源极和控制栅极。优选地，列中每个晶体管的漏极电耦合，一行中的每个晶体管的控制栅极电耦合，并且扇区中的所有晶体管的源电耦合。非易失性闪存EEPROM阵列的扇区优选地包括8行和512列的晶体管，并且块优选地包括128个垂直堆叠的扇区。

10. 发明授权

US6052305A Erasing circuit for a flash memory device having a triple well structure 有权
标题翻译：具有三重阱结构的闪存器件的擦除电路
公开(公告)号：US6052305A
公开(公告)日：2000-04-18
申请号：US143409
申请日：1998-08-28
申请人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
发明人： Tae Hum Yang , Joo Young Kim , Young Dong Joo , Jong Bae Jeong , Jong Seuk Lee , Il Hyun Choi , Mun Pyo Hong , Chae Hyun Jung
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.
摘要翻译：本发明公开了一种闪速存储器件，第一阱和第二阱形成在衬底中，多个存储单元形成在第二阱中并且布置成具有多个位线和字线的阵列。电压分别以时间间隔施加到第一阱和第二阱，使得可以防止存储单元的过度擦除和循环特性的降低。

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