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1. 发明申请

US20070008050A1 Bulk acoustic resonator including a resonance part with dimple and fabrication method therefor 失效
标题翻译：包括具有凹坑的共振部分的体声波谐振器及其制造方法
公开(公告)号：US20070008050A1
公开(公告)日：2007-01-11
申请号：US11397704
申请日：2006-04-05
申请人： Kyu-dong Jung , Jong-oh Kwon , Woon-bae Kim , In-sang Song
发明人： Kyu-dong Jung , Jong-oh Kwon , Woon-bae Kim , In-sang Song
IPC分类号： H03H9/54
CPC分类号： H03H9/173 , H03H3/02 , H03H9/174 , H03H2003/021 , H03H2003/023
摘要： A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.
摘要翻译：一种体声共振和一种用于制造体声波谐振器的方法，所述体声波谐振器包括：基板，包括限定包括空腔的预定区域的上表面; 谐振部分，其位于空腔上方并包括包括凹坑的表面; 以及将共振部分连接到基板的锚固部分。共振部包括：下电极，其包括具有预定凹坑区域的下表面和与预定凹坑区域相对的上表面; 压电层，堆叠在下电极的上表面上; 以及堆叠在压电层上的上电极。由于通过调节位置，面积和凹坑的数量来调节谐振器的振动方向，可以提高工艺自由度。

2. 发明授权

US07456709B2 Bulk acoustic resonator including a resonance part with dimple and fabrication method therefor 失效
标题翻译：包括具有凹坑的共振部分的体声波谐振器及其制造方法
公开(公告)号：US07456709B2
公开(公告)日：2008-11-25
申请号：US11397704
申请日：2006-04-05
申请人： Kyu-dong Jung , Jong-oh Kwon , Woon-bae Kim , In-sang Song
发明人： Kyu-dong Jung , Jong-oh Kwon , Woon-bae Kim , In-sang Song
IPC分类号： H03H9/15 , H03H9/54
CPC分类号： H03H9/173 , H03H3/02 , H03H9/174 , H03H2003/021 , H03H2003/023
摘要： A bulk acoustic resonance and a method for fabricating the bulk acoustic resonator, the bulk acoustic resonator including: a substrate including an upper surface defining a predetermined area including a cavity; a resonance part positioned above the cavity and including a surface comprising a dimple; and an anchor part connecting the resonance part to the substrate. The resonance part includes: a lower electrode including a lower surface including a predetermined dimpled area and an upper surface opposite to the predetermined dimpled area; a piezoelectric layer stacked on the upper surface of the lower electrode; and an upper electrode stacked on the piezoelectric layer. Because direction of the vibration of the resonator is adjustable by adjusting position, area, and the number of the dimples, process freedom can be improved.
摘要翻译：一种体声共振和一种用于制造体声波谐振器的方法，所述体声波谐振器包括：基板，包括限定包括空腔的预定区域的上表面; 谐振部分，其位于空腔上方并包括包括凹坑的表面; 以及将共振部分连接到基板的锚固部分。共振部包括：下电极，其包括具有预定凹坑区域的下表面和与预定凹坑区域相对的上表面; 压电层，堆叠在下电极的上表面上; 以及堆叠在压电层上的上电极。由于通过调节位置，面积和凹坑的数量来调节谐振器的振动方向，可以提高工艺自由度。

3. 发明申请

US20060273444A1 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US20060273444A1
公开(公告)日：2006-12-07
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/48
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

4. 发明申请

US20090166511A1 IMAGE SENSOR MODULE HAVING ELECTRIC COMPONENT AND FABRICATION METHOD THEREOF 有权
标题翻译：具有电气元件的图像传感器模块及其制造方法
公开(公告)号：US20090166511A1
公开(公告)日：2009-07-02
申请号：US12185910
申请日：2008-08-05
申请人： Jong-oh KWON , Yoon-chul Son , Kyu-dong Jung , Woon-bae Kim
发明人： Jong-oh KWON , Yoon-chul Son , Kyu-dong Jung , Woon-bae Kim
IPC分类号： G01J1/44
CPC分类号： G01J1/02 , G01J1/0204 , G01J1/0219 , G01J1/0271 , G01J1/04 , G01J1/0411 , H01L27/14618 , H01L27/14625 , H01L2924/0002 , H04N5/2253 , H04N5/2254 , H04N5/2257 , H01L2924/00
摘要： An image sensor module capable of facilitating an electrical and mechanical connection of an electric component and a fabrication thereof are disclosed. The image sensor module includes a sensor chip; at least one lens disposed above the sensor chip; at least one electric component disposed with respect to the at least one lens to adjust optical characteristics of the at least one lens; a housing accommodating and closing up the sensor chip, the at least one lens and the at least one electric component, and having an opening to expose the at least one lens to an outside thereof; and a wiring part longitudinally disposed on an inner surface of the housing, and including at least one conducting wire having a first connecting terminal exposed to the outside of the housing to allow the at least one conducting wire to electrically connect a terminal pad of the at least one electric component with an external electronic device and a second connecting terminal connected to the terminal pad of the at least one electric component.
摘要翻译：公开了能够促进电气部件的电气和机械连接及其制造的图像传感器模块。图像传感器模块包括传感器芯片; 设置在所述传感器芯片上方的至少一个透镜; 相对于所述至少一个透镜布置的至少一个电气部件，以调节所述至少一个透镜的光学特性; 容纳和封闭传感器芯片的壳体，所述至少一个透镜和所述至少一个电气部件，并且具有用于将所述至少一个透镜暴露于其外部的开口; 以及纵向设置在所述壳体的内表面上的布线部分，并且包括至少一个导线，其具有暴露于所述壳体的外部的第一连接端子，以允许所述至少一根导线电连接所述壳体的端子垫至少一个具有外部电子设备的电气部件和连接到所述至少一个电气部件的端子焊盘的第二连接端子。

5. 发明申请

US20090142050A1 MICRO SHUTTER HAVING IRIS FUNCTION, METHOD FOR MANUFACTURING THE SAME, AND MICRO CAMERA MODULE HAVING THE SAME 有权
标题翻译：具有IRIS功能的MICRO SHUTTER，其制造方法和具有该功能的微型相机模块
公开(公告)号：US20090142050A1
公开(公告)日：2009-06-04
申请号：US12134324
申请日：2008-06-06
申请人： Che-heung KIM , Woon-bae Kim , Jong-oh Kwon , Kyu-dong Jung
发明人： Che-heung KIM , Woon-bae Kim , Jong-oh Kwon , Kyu-dong Jung
IPC分类号： G03B9/28 , B05D5/12
CPC分类号： G03B9/28
摘要： A micro shutter with an iris function includes a base plate with a transparent portion formed in a circular shape corresponding to an image sensor which allows light to pass through; a plurality of rollup blades which block the light, arranged in a regular polygon at a circumference of the transparent portion on the base plate to cover the transparent portion, and each of the plurality of rollup blades to have a fixing portion fixed to the base plate and a moving portion rolled up toward the fixing portion; and a controller electrically connected with the base plate and the plurality of rollup blades which controls unrolling degrees of the plurality of rollup blades.
摘要翻译：具有虹膜功能的微型快门包括：底板，其具有与允许光通过的图像传感器相对应的圆形形状的透明部分; 多个汇集叶片，其将光线布置在基板上的透明部分的圆周上的正多边形以覆盖透明部分，并且多个汇总叶片中的每一个具有固定到基板的固定部分以及朝向固定部分卷起的移动部分; 以及与所述基板和所述多个汇总叶片电连接的控制器，其控制所述多个汇总叶片的展开度。

6. 发明授权

US08061910B2 Micro shutter having iris function, method for manufacturing the same, and micro camera module having the same 有权
标题翻译：具有虹膜功能的微型快门及其制造方法以及具有该功能的微型相机模块
公开(公告)号：US08061910B2
公开(公告)日：2011-11-22
申请号：US12134324
申请日：2008-06-06
申请人： Che-heung Kim , Woon-bae Kim , Jong-oh Kwon , Kyu-dong Jung
发明人： Che-heung Kim , Woon-bae Kim , Jong-oh Kwon , Kyu-dong Jung
IPC分类号： G03B9/34
CPC分类号： G03B9/28
摘要： A micro shutter with an iris function includes a base plate with a transparent portion formed in a circular shape corresponding to an image sensor which allows light to pass through; a plurality of rollup blades which block the light, arranged in a regular polygon at a circumference of the transparent portion on the base plate to cover the transparent portion, and each of the plurality of rollup blades to have a fixing portion fixed to the base plate and a moving portion rolled up toward the fixing portion; and a controller electrically connected with the base plate and the plurality of rollup blades which controls unrolling degrees of the plurality of rollup blades.
摘要翻译：具有虹膜功能的微型快门包括：底板，其具有与允许光通过的图像传感器相对应的圆形形状的透明部分; 多个汇集叶片，其将光线布置在基板上的透明部分的圆周上的正多边形以覆盖透明部分，并且多个汇总叶片中的每一个具有固定到基板的固定部分以及朝向固定部分卷起的移动部分; 以及与所述基板和所述多个汇总叶片电连接的控制器，其控制所述多个汇总叶片的展开度。

7. 发明授权

US07663083B2 Image sensor module having electric component and fabrication method thereof 有权
标题翻译：具有电子部件的图像传感器模块及其制造方法
公开(公告)号：US07663083B2
公开(公告)日：2010-02-16
申请号：US12185910
申请日：2008-08-05
申请人： Jong-oh Kwon , Yoon-chul Son , Kyu-dong Jung , Woon-bae Kim
发明人： Jong-oh Kwon , Yoon-chul Son , Kyu-dong Jung , Woon-bae Kim
IPC分类号： H01L23/52
CPC分类号： G01J1/02 , G01J1/0204 , G01J1/0219 , G01J1/0271 , G01J1/04 , G01J1/0411 , H01L27/14618 , H01L27/14625 , H01L2924/0002 , H04N5/2253 , H04N5/2254 , H04N5/2257 , H01L2924/00
摘要： An image sensor module capable of facilitating an electrical and mechanical connection of an electric component and a fabrication thereof are disclosed. The image sensor module includes a sensor chip; at least one lens disposed above the sensor chip; at least one electric component disposed with respect to the at least one lens to adjust optical characteristics of the at least one lens; a housing accommodating and closing up the sensor chip, the at least one lens and the at least one electric component, and having an opening to expose the at least one lens to an outside thereof; and a wiring part longitudinally disposed on an inner surface of the housing, and including at least one conducting wire having a first connecting terminal exposed to the outside of the housing to allow the at least one conducting wire to electrically connect a terminal pad of the at least one electric component with an external electronic device and a second connecting terminal connected to the terminal pad of the at least one electric component.
摘要翻译：公开了能够促进电气部件的电气和机械连接及其制造的图像传感器模块。图像传感器模块包括传感器芯片; 设置在所述传感器芯片上方的至少一个透镜; 相对于所述至少一个透镜布置的至少一个电气部件，以调节所述至少一个透镜的光学特性; 容纳和封闭传感器芯片的壳体，所述至少一个透镜和所述至少一个电气部件，并且具有用于将所述至少一个透镜暴露于其外部的开口; 以及纵向设置在所述壳体的内表面上的布线部分，并且包括至少一个导线，其具有暴露于所述壳体的外部的第一连接端子，以允许所述至少一根导线电连接所述壳体的端子垫至少一个具有外部电子设备的电气部件和连接到所述至少一个电气部件的端子焊盘的第二连接端子。

8. 发明授权

US07408257B2 Packaging chip and packaging method thereof 失效
标题翻译：包装芯片及其包装方法
公开(公告)号：US07408257B2
公开(公告)日：2008-08-05
申请号：US11390220
申请日：2006-03-28
申请人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
发明人： Kyu-dong Jung , Woon-bae Kim , In-sang Song , Moon-chul Lee , Jun-sik Hwang , Suk-jin Ham
IPC分类号： H01L23/04
CPC分类号： H01L23/055 , H01L23/04 , H01L27/14618 , H01L2224/16
摘要： A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.
摘要翻译：提供电路模块封装的封装芯片和封装电路模块的方法。包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔，将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

9. 发明授权

US07786573B2 Packaging chip having interconnection electrodes directly connected to plural wafers 有权
标题翻译：具有直接连接到多个晶片的互连电极的封装芯片
公开(公告)号：US07786573B2
公开(公告)日：2010-08-31
申请号：US11481012
申请日：2006-07-06
申请人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
发明人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
IPC分类号： H01L23/34 , H01R12/16 , H05K1/11
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H03H9/0547
摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
摘要翻译：形成有多个晶片的封装芯片。封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。多个晶片中的至少一个或多个在其上安装预定的电路装置。此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

10. 发明申请

US20070013058A1 Packaging chip having interconnection electrodes directly connected to plural wafers and fabrication method therefor 有权
标题翻译：具有直接连接到多个晶片的互连电极的封装芯片及其制造方法
公开(公告)号：US20070013058A1
公开(公告)日：2007-01-18
申请号：US11481012
申请日：2006-07-06
申请人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
发明人： Min-seog Choi , Kae-dong Back , In-sang Song , Woon-bae Kim , Byung-gil Jeong , Kyu-dong Jung
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/481 , H01L25/50 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H03H9/0547
摘要： A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
摘要翻译：形成有多个晶片的封装芯片。封装芯片包括依次堆叠的多个晶片和从多个晶片的最上面的晶片的上表面直接连接多个晶片到另一个晶片的多个互连电极。多个晶片中的至少一个或多个在其上安装预定的电路装置。此外，多个晶片的至少一个或多个晶片具有预定尺寸的空腔。同时，封装芯片还包括独立地布置在最上面的晶片的上表面上并分别电连接到多个互连电极的多个焊盘。因此，本发明可以提高封装芯片的性能和可靠性，并提高制造成品率。

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