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1. 发明授权

US07323407B2 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material 有权
标题翻译：使用扩散阻挡层对基材的微电子器件的双镶嵌互连的方法
公开(公告)号：US07323407B2
公开(公告)日：2008-01-29
申请号：US11195404
申请日：2005-08-02
申请人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
发明人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
IPC分类号： H01L21/311 , H01L23/52
CPC分类号： H01L21/76808 , H01L21/02134 , H01L21/3124 , H01L21/76826
摘要： Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0
摘要翻译：提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填料填充通孔 y，其中x和y满足关系x + y = 1和0

2. 发明申请

US20060063376A1 Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material 有权
标题翻译：使用扩散阻挡层对基材的微电子器件的双镶嵌互连的方法
公开(公告)号：US20060063376A1
公开(公告)日：2006-03-23
申请号：US11195404
申请日：2005-08-02
申请人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
发明人： Kyoung-woo Lee , Jae-yeol Maeng , Jae-hak Kim , Il-whan Oh , Hong-jae Shin
IPC分类号： H01L21/4763 , H01L21/31
CPC分类号： H01L21/76808 , H01L21/02134 , H01L21/3124 , H01L21/76826
摘要： Methods of fabricating dual damascene interconnections suitable for use in microelectronic devices and similar applications using a diffusion barrier layer to protect against base materials during processing are provided. The methods include the steps of: filling a via with a hydrogen silsesquioxane (HSQ)-based filler as expressed by the general chemical formula: (RSiO3/2)x(HSiO3/2)y, wherein x and y satisfy the relationships x+y=1 and 0
摘要翻译：提供了适用于微电子器件的双镶嵌互连的方法和使用扩散阻挡层在加工期间防止基底材料的类似应用。所述方法包括以下步骤：用以通式（RSiO 3/2/2）x（HSiO 3/2/2）表示的氢倍半硅氧烷（HSQ））填充通孔 y，其中x和y满足关系x + y = 1和0

3. 发明授权

US07183195B2 Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler 有权
标题翻译：使用混合低k电介质和无碳无机填料制造微电子器件的双镶嵌互连的方法
公开(公告)号：US07183195B2
公开(公告)日：2007-02-27
申请号：US10625007
申请日：2003-07-23
申请人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
发明人： Kyoung-woo Lee , Soo-geun Lee , Wan-jae Park , Jae-hak Kim , Hong-jae Shin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of fabricating dual damascene interconnections is provided. A dual damascene region is formed in a hybrid dielectric layer having a dielectric constant of 3.3 or less, and a carbon-free inorganic material is used as a via filler. The present invention improves electrical properties of dual damascene interconnections and minimizes defects.
摘要翻译：提供了一种制造双镶嵌互连的方法。在具有3.3或更小的介电常数的混合电介质层中形成双镶嵌区域，并且使用无碳无机材料作为通孔填料。本发明改进了双镶嵌互连的电性能并使缺陷最小化。

4. 发明授权

US06815331B2 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US06815331B2
公开(公告)日：2004-11-09
申请号：US10392710
申请日：2003-03-20
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L214163
CPC分类号： H01L21/76808 , H01L21/76813
摘要： Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; forming an interlayer dielectric layer on the stopper layer; forming a hard mask layer on the interlayer dielectric layer; forming a first photoresist pattern on the hard mask layer, the first photoresist pattern having a first opening corresponding to the conductive layer; etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask to form a via hole in the interlayer dielectric layer through which a portion of the stopper layer is exposed; removing the first photoresist pattern; filling the via hole with an intermediary material layer; etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region, wherein the hard mask pattern comprises a second opening that overlaps the entire via hole or at least a portion of the via hole; removing the intermediary material layer from the via hole; forming the wiring region by etching a portion of the interlayer dielectric layer using the hard mask pattern as an etching mask; removing a portion of the stopper layer exposed by the via hole; and filling the via hole and the wiring region with a conductive material.
摘要翻译：使用双镶嵌工艺在半导体器件中形成金属布线层的方法。一方面，在半导体器件中形成金属布线的方法包括：在其上形成有导电层的半导体衬底上形成阻挡层; 在所述阻挡层上形成层间绝缘层; 在所述层间介质层上形成硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂图案，所述第一光致抗蚀剂图案具有对应于所述导电层的第一开口; 使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，以在阻挡层的一部分暴露的层间绝缘层中形成通孔; 去除第一光致抗蚀剂图案; 用中间材料层填充通孔; 蚀刻硬掩模层的一部分以形成限定布线区域的硬掩模图案，其中硬掩模图案包括与整个通孔或通孔的至少一部分重叠的第二开口; 从所述通孔中去除所述中间材料层; 通过使用硬掩模图案作为蚀刻掩模蚀刻层间电介质层的一部分来形成布线区域; 去除由通孔露出的阻挡层的一部分; 以及用导电材料填充所述通孔和所述布线区域。

5. 发明申请

US20090280637A1 Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
标题翻译：包括超低介电常数层的半导体器件的制造方法
公开(公告)号：US20090280637A1
公开(公告)日：2009-11-12
申请号：US12453326
申请日：2009-05-07
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Jae-ouk Choo
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31695
摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层半导体器件。该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔，形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

6. 发明授权

US06828229B2 Method of manufacturing interconnection line in semiconductor device 有权
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US06828229B2
公开(公告)日：2004-12-07
申请号：US10081661
申请日：2002-02-22
申请人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
发明人： Soo-geun Lee , Hong-jae Shin , Kyoung-woo Lee , Jae-hak Kim
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31116 , H01L21/31144
摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.
摘要翻译：提供了一种在半导体器件中形成互连线的方法。在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。在第一蚀刻停止件上形成第一层间绝缘层。在第一层间绝缘层上形成第二蚀刻阻挡层。在第二蚀刻停止件上形成第二层间绝缘层。使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。保护层被去除。位于通孔底部的第一蚀刻停止部分被去除。形成填充通孔和沟槽并与下导电层电连接的上导电层。

7. 发明授权

US06861347B2 Method for forming metal wiring layer of semiconductor device 有权
标题翻译：用于形成半导体器件的金属布线层的方法
公开(公告)号：US06861347B2
公开(公告)日：2005-03-01
申请号：US10114274
申请日：2002-04-02
申请人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
发明人： Kyoung-woo Lee , Hong-jae Shin , Jae-hak Kim , Soo-geun Lee
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813 , H01L21/76835
摘要： A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.
摘要翻译：提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。去除第一光致抗蚀剂图案。在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。同时去除第二光致抗蚀剂图案和有机材料层。通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

8. 发明授权

US07687915B2 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US07687915B2
公开(公告)日：2010-03-30
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/522
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

9. 发明申请

US20090096104A1 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US20090096104A1
公开(公告)日：2009-04-16
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/532
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

10. 发明授权

US07598168B2 Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer 失效
标题翻译：制造双镶嵌互连的方法和用于剥离牺牲层的蚀刻剂
公开(公告)号：US07598168B2
公开(公告)日：2009-10-06
申请号：US11033208
申请日：2005-01-11
申请人： Sang-cheol Han , Kyoung-woo Lee , Mi-young Kim
发明人： Sang-cheol Han , Kyoung-woo Lee , Mi-young Kim
IPC分类号： H01L21/4763 , H01L21/461
CPC分类号： H01L21/76808 , H01L21/31111 , H01L21/31144 , H01L21/76829
摘要： A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NH4F, HF, H2O and a surfactant.
摘要翻译：提供了形成双镶嵌半导体互连的方法和特别适于在双镶嵌制造工艺中剥离牺牲层而不对双镶嵌图案造成损伤的蚀刻剂组合物。该方法包括在其上形成有下金属布线的半导体衬底的表面上顺序地形成第一蚀刻停止层，第一金属间电介质，第二金属间电介质和覆盖层; 蚀刻第一金属间电介质，第二金属间电介质和封盖层以形成通孔; 在通孔内形成牺牲层; 蚀刻牺牲层，第二金属间电介质和覆盖层以形成沟槽; 使用包括NH 4 F，HF，H 2 O和表面活性剂的蚀刻剂组合物除去残留在通孔周围的牺牲层; 以及在由此形成的包括通孔和沟槽的双镶嵌图案中形成上金属布线。用于剥离前述双镶嵌工艺中的牺牲层的优选蚀刻剂组合物基本上由NH 4 F，HF，H 2 O和表面活性剂组成。

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