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    • 3. 发明授权
    • Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same
    • 电线的接触结构及其制造方法,以及包括接触结构的薄膜晶体管基板及其制造方法
    • US07659625B2
    • 2010-02-09
    • US12333973
    • 2008-12-12
    • Seung-Taek LimMun-Pyo HongNam-Seok RohYoung-Joo SongSang-Ki KwakKwon-Young ChoiKeun-Kyu Song
    • Seung-Taek LimMun-Pyo HongNam-Seok RohYoung-Joo SongSang-Ki KwakKwon-Young ChoiKeun-Kyu Song
    • H01L23/48
    • G02F1/13458G02F1/136227G02F1/136286G02F2001/13629H01L21/76805H01L21/76816H01L23/53223H01L27/124H01L2924/0002H01L2924/00
    • In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
    • 在制造用于液晶显示器的薄膜晶体管阵列基板的方法中,栅极线组件在沿水平方向前进的基底上形成有铬基底层和基于铝合金的超层。 栅极线组件具有栅极线,栅电极和栅极焊盘。 栅极绝缘层沉积在绝缘基板上,使得栅极绝缘层覆盖栅极线组件。 在栅极绝缘层上依次形成半导体层和欧姆接触层。 数据线组件在欧姆接触层上形成有铬基底层和基于铝合金的超层。 数据线组件具有跨越栅极线,源电极,漏电极和数据焊盘的数据线。 保护层沉积到衬底上,并被图案化,从而形成露出漏电极,栅极焊盘和数据焊盘的接触孔。 用于栅极线组件和数据线组件的下层的侧壁通过接触孔暴露。 将基于IZO的层沉积到衬底上并构图,从而形成像素电极,辅助栅极焊盘和辅助数据焊盘。 像素电极连接到漏电极的侧壁,辅助栅极和数据焊盘连接到栅极和数据焊盘的侧壁。
    • 5. 发明授权
    • Method of manufacturing a thin film transistor array panel
    • 制造薄膜晶体管阵列面板的方法
    • US07459323B2
    • 2008-12-02
    • US11512805
    • 2006-08-30
    • Min-Wook ParkSang-Jin JeonJung-Joon ParkJeong-Young LeeBum-Ki BaekSe-Hwan YuSang-Ki KwakHan-Ju LeeKwon-Young Choi
    • Min-Wook ParkSang-Jin JeonJung-Joon ParkJeong-Young LeeBum-Ki BaekSe-Hwan YuSang-Ki KwakHan-Ju LeeKwon-Young Choi
    • H01L21/00
    • G02F1/1368G02F1/1339
    • A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode and a pair of redundant electrodes on the first and the second portions of the lower conductive film, respectively, the redundant electrodes exposing a part of the second portion of the lower conductive film; removing the exposed part of the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.
    • 提供一种制造薄膜晶体管阵列面板的方法,包括:在基板上形成栅极线; 在栅极线上依次沉积栅极绝缘层和半导体层; 在半导体层上沉积下导电膜和上导电膜; 对上导电膜,下导电膜和半导体层进行光蚀刻; 沉积钝化层; 对所述钝化层进行光蚀刻以暴露所述上导电膜的第一和第二部分; 去除上导电膜的第一和第二部分以暴露下导电膜的第一和第二部分; 在下导电膜的第一和第二部分上形成像素电极和一对冗余电极,所述冗余电极暴露下导电膜的第二部分的一部分; 去除下导电膜的第二部分的暴露部分以暴露半导体层的一部分; 以及在半导体层的暴露部分上形成柱状间隔物。
    • 7. 发明授权
    • Liquid crystal display having an electrostatic protection circuit
    • 具有静电保护电路的液晶显示器
    • US06384878B1
    • 2002-05-07
    • US09415456
    • 1999-10-14
    • Sang-Ki Kwak
    • Sang-Ki Kwak
    • G02F11333
    • G02F1/136204
    • Gate lines and dummy gate lines are respectively located inside a display area and outside the display area. Data lines are arranged perpendicular to and are insulated from the gate lines and the dummy gate lines. A semiconductor layer and a dummy semiconductor layer respectively correspond to and are insulated from the gate line and the dummy gate line. Source electrodes, which respectively overlap an edge of the respective semiconductor layers, and a dummy source electrode, which overlaps an edge of the dummy semiconductor layer are extended from the data line. Drain electrodes, which respectively overlap the edge of the respective semiconductor layers, and a dummy drain electrode, which overlaps the edge of the dummy semiconductor layer, are respectively formed opposite the source electrodes and the dummy source electrode. In this structure, since the dummy drain electrode overlaps the dummy gate line, a dummy storage capacitor is formed therebetween. A pixel electrode is located in a pixel defined by the intersection of the gate lines and the data lines and is electrically connected to the drain electrode. Moreover, the pixel electrode overlaps the gate lines so that a storage capacitor is formed in the pixel. In this invention, a ratio of storage capacitance of one storage capacitor to dummy storage capacitance of one dummy storage capacitor is controlled to be 2.23 and lower.
    • 栅极线和虚拟栅极线分别位于显示区域内和显示区域的外部。 数据线布置成与栅极线和虚拟栅极线垂直并与其绝缘。 半导体层和虚拟半导体层分别对应于栅极线和虚拟栅极线并与绝缘栅极线绝缘。 与该半导体层的边缘分别重叠的源电极和与伪半导体层的边缘重叠的虚拟源电极从数据线延伸。 分别与各半导体层的边缘重叠的漏极电极和与虚设半导体层的边缘重叠的虚设漏极电极分别与源电极和虚拟源电极相对。 在该结构中,由于虚设漏电极与伪栅极线重叠,所以在其间形成虚拟存储电容。 像素电极位于由栅极线和数据线的交点限定的像素中,并与漏电极电连接。 此外,像素电极与栅极线重叠,使得在像素中形成存储电容器。 在本发明中,将一个存储电容器的存储电容与一个虚拟存储电容器的虚拟存储电容的比率控制在2.23以下。
    • 8. 发明授权
    • Display apparatus
    • 显示装置
    • US09001162B2
    • 2015-04-07
    • US13104280
    • 2011-05-10
    • Sang-Yong NoYoon-Jang KimSang-Ki Kwak
    • Sang-Yong NoYoon-Jang KimSang-Ki Kwak
    • G09G3/36
    • G09G3/3648G09G2300/0852
    • A display apparatus includes a plurality of pixels. Each pixel includes a first sub-pixel that is charged with a data signal corresponding to an input gray-scale, in response to a gate signal, and a second sub-pixel that is charged with the data signal in response to the gate signal. A boost capacitor is disposed between the first and second sub-pixels. The boost capacitor increases the voltage of the signal charged in the first sub-pixel and decreases the voltage of the signal charged in the second sub-pixel. Each pixel further includes an initializing device to initialize a first electrode of the boost capacitor and a switching device to change an electric potential of the first electrode of the boost capacitor.
    • 显示装置包括多个像素。 每个像素包括响应于门信号而充满与输入灰度级对应的数据信号的第一子像素,以及响应于门信号对数据信号充电的第二子像素。 升压电容器设置在第一和第二子像素之间。 升压电容器增加在第一子像素中充电的信号的电压,并降低在第二子像素中充电的信号的电压。 每个像素还包括初始化升压电容器的第一电极的初始化装置和改变升压电容器的第一电极的电位的开关装置。
    • 10. 发明授权
    • Liquid crystal display
    • 液晶显示器
    • US08400588B2
    • 2013-03-19
    • US12900433
    • 2010-10-07
    • Byung-Duk YangEun-Guk LeeSang-Ki KwakDong-Yoon KimYun-Jong Yeo
    • Byung-Duk YangEun-Guk LeeSang-Ki KwakDong-Yoon KimYun-Jong Yeo
    • G02F1/1335
    • G02F1/1335
    • A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate; a first signal line disposed on the first substrate, a thin film transistor connected with the first signal line, a first color filter and a second color filter disposed on the first substrate; a colored member disposed on the first color filter and the second color filter; and a pixel electrode disposed on the first color filter and the second color filter and the colored member, wherein the first color filter and the second color filter are partially overlapped with each other and the height of the colored member disposed at the overlap between the first color filter and the second color filter is greater than the height of the colored member disposed not at the overlap.
    • 根据本发明的示例性实施例的液晶显示器包括:第一基板; 设置在第一基板上的第一信号线,与第一信号线连接的薄膜晶体管,设置在第一基板上的第一滤色器和第二滤色器; 设置在所述第一滤色器和所述第二滤色器上的着色部件; 以及设置在所述第一滤色器和所述第二滤色器和所述着色部件上的像素电极,其中所述第一滤色器和所述第二滤色器彼此部分重叠,并且所述着色部件的高度设置在所述第一滤色器 滤色器和第二滤色器大于被设置为不重叠的着色部件的高度。