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1. 发明申请

US20090292972A1 Error correction apparatus, method thereof and memory device comprising the apparatus 有权
标题翻译：误差校正装置及其方法和包括该装置的存储装置
公开(公告)号：US20090292972A1
公开(公告)日：2009-11-26
申请号：US12453813
申请日：2009-05-22
申请人： Kwang Soo Seol , Sung Il Park , Kyoung Lae Cho
发明人： Kwang Soo Seol , Sung Il Park , Kyoung Lae Cho
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.
摘要翻译：提供了一种纠错装置，其方法和包括该装置的存储装置。误差校正装置可以包括：确定单元，被配置为确定从多级单元（MLC）读取和提取的读取字中的错误数是否存在于纠错能力范围内; 读取电压控制单元，被配置为当读取字中的错误数量超出纠错能力范围时，增加或减小施加到MLC的读取电压; 以及码字确定单元，被配置为基于读取电压的增加或减少来分析位错误，并且基于所选择的读取错误模式来选择与分析的位错误相对应的码字。通过这样，可以有效地校正当长时间保持存储器件的数据时发生的读取错误。

2. 发明申请

US20090292973A1 Memory device and method of storing data 有权
标题翻译：存储设备和存储数据的方法
公开(公告)号：US20090292973A1
公开(公告)日：2009-11-26
申请号：US12453814
申请日：2009-05-22
申请人： Kwang Soo Seol , Sung Il Park , Kyoung Lae Cho , In Sung Joe
发明人： Kwang Soo Seol , Sung Il Park , Kyoung Lae Cho , In Sung Joe
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/611 , G06F11/1072 , G11C7/1006 , G11C11/5642 , G11C16/26 , G11C29/00 , H03M13/13 , H03M13/15 , H03M13/27 , H03M13/2732 , H03M13/2906 , H03M13/3707 , H03M13/3715 , H03M13/47
摘要： Memory devices and/or methods of storing memory data bits may be provided. A memory device may include a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it may be possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.
摘要翻译：可以提供存储器件和/或存储存储器数据位的方法。存储器装置可以包括包括多个MLC的多级单元（MLC）阵列，错误校正单元，被配置为对要记录在MLC中的数据进行编码，其中编码数据被转换以将编码数据转换为码字，错误模式分析单元，被配置为分析与码字中包含的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将所分析的第一数据模式转换为第二数据模式。根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。

3. 发明授权

US08301978B2 Memory device and method of storing data with error correction using codewords 有权
标题翻译：使用码字进行纠错的存储装置和存储数据的方法
公开(公告)号：US08301978B2
公开(公告)日：2012-10-30
申请号：US12453814
申请日：2009-05-22
申请人： Kwang Soo Seol , Sung II Park , Kyoung Lae Cho , In Sung Joe
发明人： Kwang Soo Seol , Sung II Park , Kyoung Lae Cho , In Sung Joe
IPC分类号： G11C29/00
CPC分类号： H03M13/611 , G06F11/1072 , G11C7/1006 , G11C11/5642 , G11C16/26 , G11C29/00 , H03M13/13 , H03M13/15 , H03M13/27 , H03M13/2732 , H03M13/2906 , H03M13/3707 , H03M13/3715 , H03M13/47
摘要： Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.
摘要翻译：提供了存储器件和/或存储存储器数据位的方法。存储器件包括包括多个MLC的多电平单元（MLC）阵列，纠错单元，被配置为编码要记录在MLC中的数据，其中编码数据被转换以将编码数据转换为码字，错误模式分析单元，被配置为分析与包括在码字中的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将分析的第一数据模式转换为第二数据模式。根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。

4. 发明授权

US08560901B2 Apparatus, method and memory device for error correction by increasing or decreasing a read voltage and analyzing frequency information for a read error pattern 有权
标题翻译：用于通过增加或减少读取电压并分析读取错误模式的频率信息进行纠错的装置，方法和存储装置
公开(公告)号：US08560901B2
公开(公告)日：2013-10-15
申请号：US12453813
申请日：2009-05-22
申请人： Kwang Soo Seol , Sung II Park , Kyoung Lae Cho
发明人： Kwang Soo Seol , Sung II Park , Kyoung Lae Cho
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2211/5634
摘要： An error correction apparatus, a method thereof, and a memory device including the apparatus are provided. The error correction apparatus may include: a determination unit configured to determine whether a number of errors in a read word being read and extracted from a multi-level cell (MLC) exists in an error correcting capability range; a read voltage control unit configured to either increase or decrease a read voltage applied to the MLC when the number of errors in the read word is outside the error correcting capability range; and a codeword determination unit configured to analyze a bit error based on the increase or decrease of the read voltage, and to select a codeword corresponding to the analyzed bit error based on a selected read error pattern. Through this, it may be possible to efficiently correct a read error that occurs when the data of the memory device is maintained for a long time.
摘要翻译：提供了一种纠错装置，其方法和包括该装置的存储装置。误差校正装置可以包括：确定单元，被配置为确定从多级单元（MLC）读取和提取的读取字中的错误数是否存在于纠错能力范围内; 读取电压控制单元，被配置为当读取字中的错误数量超出纠错能力范围时，增加或减小施加到MLC的读取电压; 以及码字确定单元，被配置为基于读取电压的增加或减少来分析位错误，并且基于所选择的读取错误模式来选择与分析的位错误相对应的码字。通过这样，可以有效地校正当长时间保持存储器件的数据时发生的读取错误。

5. 发明授权

US09478560B2 Memory device 有权
公开(公告)号：US09478560B2
公开(公告)日：2016-10-25
申请号：US14940137
申请日：2015-11-12
申请人： Kwang Soo Seol , JinTae Kang , Seong Soon Cho
发明人： Kwang Soo Seol , JinTae Kang , Seong Soon Cho
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115 , H01L29/792 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/06 , H01L29/41
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L29/0676 , H01L29/413 , H01L29/42332 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

6. 发明授权

US08530959B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US08530959B2
公开(公告)日：2013-09-10
申请号：US13198234
申请日：2011-08-04
申请人： Sung-Il Chang , Youngwoo Park , Kwang Soo Seol
发明人： Sung-Il Chang , Youngwoo Park , Kwang Soo Seol
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.
摘要翻译：提供三维半导体器件。一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层的半导体图案以将半导体图案连接到基板。

7. 发明申请

US20110079839A1 Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same 审中-公开
标题翻译：具有降低存储容量泄漏的易感性的非易失性存储器件及其形成方法
公开(公告)号：US20110079839A1
公开(公告)日：2011-04-07
申请号：US12894863
申请日：2010-09-30
申请人： Fayrushin Albert , Kwang Soo Seol , Jaeduk Lee
发明人： Fayrushin Albert , Kwang Soo Seol , Jaeduk Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/4234 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7883 , H01L29/792
摘要： Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.
摘要翻译：提供一种半导体器件。半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。隧道绝缘层设置在衬底上。电荷存储图案设置在隧道绝缘层上。电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

8. 发明授权

US07888857B2 Light emitting device with three-dimensional structure and fabrication method thereof 失效
标题翻译：具有三维结构的发光器件及其制造方法
公开(公告)号：US07888857B2
公开(公告)日：2011-02-15
申请号：US11534710
申请日：2006-09-25
申请人： Jae Young Choi , Byoung Lyong Choi , Dong Kee Yi , Kwang Soo Seol , Seong Jae Choi
发明人： Jae Young Choi , Byoung Lyong Choi , Dong Kee Yi , Kwang Soo Seol , Seong Jae Choi
IPC分类号： H01J63/04 , H01J1/62
CPC分类号： H01L29/06 , B82Y20/00 , B82Y30/00 , H01L51/502 , H01L51/52
摘要： A three-dimensional light emitting device and a method for fabricating the light emitting device are provided. The light emitting device comprises a substrate and a semiconductor nanoparticle layer wherein the substrate is provided with a plurality of three-dimensional recesses and the surface having the recesses is coated with semiconductor nanoparticles. According to the three-dimensional light emitting device, the formation of the semiconductor nanoparticles on the surface of the recessed substrate increases the light emitting area and enhances the luminescence intensity, leading to an increase in the amount of light emitted from the light emitting device per unit area. Therefore, the three-dimensional light emitting device has the advantage of improved luminescence efficiency.
摘要翻译：提供三维发光器件和制造发光器件的方法。发光器件包括衬底和半导体纳米颗粒层，其中衬底设置有多个三维凹槽，并且具有凹陷的表面涂覆有半导体纳米颗粒。根据三维发光装置，在凹陷基板的表面上形成半导体纳米颗粒增加发光面积并增强发光强度，导致从发光装置发射的光量增加单位面积因此，三维发光装置具有提高发光效率的优点。

9. 发明授权

US09111617B2 Three-dimensional semiconductor memory device 有权
标题翻译：三维半导体存储器件
公开(公告)号：US09111617B2
公开(公告)日：2015-08-18
申请号：US13585963
申请日：2012-08-15
申请人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
发明人： Sunil Shim , Jang-gn Yun , Jeonghyuk Choi , Kwang Soo Seol , Jaehoon Jang , Jungdal Choi
IPC分类号： H01L29/78 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0466 , G11C16/0483 , H01L23/535 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.
摘要翻译：提供一种半导体存储器件，包括形成在衬底上的第一和第二单元串，第一和第二单元串共同连接到位线，其中第一和第二单元串中的每一个包括地选择单元，存储单元和第一和第二串选择单元，其顺序地形成在要连接的基板上，其中，所述接地选择单元连接到地选择线，所述存储单元连接到字线，所述第一串选择单元连接到第一串选择线，第二串选择单元连接到第二串选择线，并且其中第一单元串的第二串选择单元具有沟道掺杂区。

10. 发明授权

US08791520B2 Non-volatile memory devices having a floating gate cap between a floating gate and a gate insulating layer 有权
标题翻译：在浮置栅极和栅极绝缘层之间具有浮动栅极盖的非易失性存储器件
公开(公告)号：US08791520B2
公开(公告)日：2014-07-29
申请号：US12986553
申请日：2011-01-07
申请人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
发明人： Jaeduk Lee , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要翻译：提供了非易失性存储器件及其形成方法。隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。控制栅极设置在栅极电介质图案上。

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