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1. 发明申请

US20100127747A1 DIGITALLY CONTROLLED OSCILLATOR WITH THE WIDE OPERATION RANGE 有权
标题翻译：数字控制振荡器与宽操作范围
公开(公告)号：US20100127747A1
公开(公告)日：2010-05-27
申请号：US12364173
申请日：2009-02-02
申请人： Kwang Hee CHOI , Hong June PARK
发明人： Kwang Hee CHOI , Hong June PARK
IPC分类号： H03H11/26
CPC分类号： H03L7/10 , H03K3/0315 , H03K2005/00058 , H03K2005/00221 , H03L7/0995 , H03L7/0998 , H03L2207/06
摘要： There is provided a digitally controlled oscillator, which is capable of widening its operation range with maintaining its resolution and the maximum frequency at which it operates. The digitally controlled oscillator includes a phase compensation block, a coarse block, and a fine block. The phase compensation block 510 generating a PLL signal PLLCLK and a first clock signal CLK1 which has the same phase and frequency as the PLL signal, in response to a phase control signal DISABLE and a fourth clock signal CLK4. The coarse block 520 generating a second clock signal CLK2 and a third clock signal CLK3 which results from delaying the PLL signal PLLCLK and the first clock signal CLK1 for a given time, in response to a m(integer)-bit coarse A control signal COAR_A and an (m−1)-bit coarse B control signal COAR_B. The fine block generating the fourth clock signal CLK4 by applying interpolation to the second clock signal CLK2 and the third clock signal CLK3 in response to an n(integer)-bit first fine control signal FCB and a n-bit second fine control signal FC.
摘要翻译：提供了数字控制的振荡器，其能够在保持其分辨率和操作的最大频率的情况下扩大其操作范围。数字控制振荡器包括相位补偿块，粗块和精细块。响应于相位控制信号DISABLE和第四时钟信号CLK4，相位补偿块510产生PLL信号PLLCLK和与PLL信号具有相同相位和频率的第一时钟信号CLK1。粗块520产生第二时钟信号CLK2和第三时钟信号CLK3，其响应于am（整数）位粗A控制信号COAR_A，延迟PLL信号PLLCLK和第一时钟信号CLK1给定时间，（m-1）位粗B控制信号COAR_B。精细块响应于n（整数）位第一精细控制信号FCB和n位第二精细控制信号FC，通过对第二时钟信号CLK2和第三时钟信号CLK3施加内插来产生第四时钟信号CLK4。

2. 发明申请

US20070171967A1 INTERGRATING RECEIVER HAVING ADAPTIVE FEEDBACK EQUALIZER FUNCTION TO SIMULTANEOUSLY REMOVE INTER-SYMBOL INTERFERENCE AND HIGH FREQUENCY NOISES AND SYSTEM HAVING THE SAME 有权
标题翻译：具有适应性反馈均衡器功能的接收器同时移除同步干扰和高频噪声以及具有相同功能的系统
公开(公告)号：US20070171967A1
公开(公告)日：2007-07-26
申请号：US11623517
申请日：2007-01-16
申请人： Seung Jun BAE , Hong June PARK
发明人： Seung Jun BAE , Hong June PARK
IPC分类号： H03H7/30 , H04B1/10
CPC分类号： H04L25/03057
摘要： Provided is an integrating receiver having an adaptive decision feedback equalizer function and a system having the same. The integrating receiver can simultaneously remove an inter-symbol interference (ISI) and high frequency noises in a high speed DRAM data transmission system. The integrating receiver reduces a probability of wrong decision of data in a state in which the ISI that exists in a channel is removed so as to increase a signal-to-noise ratio (SNR) of a receiver, so that a maximum operation speed increases even in an environment with heavy noises. There is also provided a method of obtaining an equalizer coefficient suitable for the integrating receiver and a method of obtaining a reference voltage by using an integrator in a single ended transmission method. In addition, in order to increase a decision feedback equalizer speed, a look-ahead method is used. In this method, flip flops with a high speed including multiplexers are used. Accordingly, the present invention can be applied to not only a DRAM interface system but also a serial communication between chips.
摘要翻译：提供一种具有自适应判决反馈均衡器功能的积分接收器和具有该自适应判决反馈均衡器功能的系统。积分接收器可以同时消除高速DRAM数据传输系统中的符号间干扰（ISI）和高频噪声。积分接收器在存在于信道中的ISI被去除的状态中降低数据错误判定的可能性，以增加接收机的信噪比（SNR），从而最大运算速度增加即使在噪音很大的环境中也是如此。还提供了一种获得适合于积分接收器的均衡器系数的方法以及通过使用单端传输方法中的积分器来获得参考电压的方法。另外，为了增加判定反馈均衡器的速度，使用先行方法。在这种方法中，使用包括多路复用器的具有高速度的触发器。因此，本发明不仅可以应用于DRAM接口系统，还可以应用于芯片之间的串行通信。

3. 发明申请

US20130077445A1 ANALOG BEAMFORMER OF ULTRASONIC DIAGNOSIS APPARATUS 审中-公开
标题翻译：超声波诊断装置的模拟光束
公开(公告)号：US20130077445A1
公开(公告)日：2013-03-28
申请号：US13620128
申请日：2012-09-14
申请人： Ji Yong UM , Hong June PARK , Jae Hwan KIM
发明人： Ji Yong UM , Hong June PARK , Jae Hwan KIM
IPC分类号： H04B1/16
CPC分类号： G01S7/52026 , A61B8/483 , G10K11/346
摘要： An analog beamformer of an ultrasonic diagnosis apparatus includes: a plurality of unit analog beamformers allocated to two or more focal points, respectively, and configured to beamform signals received from the respective focal points through transducer elements and output the beamformed signals; an analog multiplexer configured to sequentially select the output signals of the unit analog beamformers and generate a final output signal; a clock generator configured to provide a clock signal required for the unit analog beamformers; and a processor configured to provide information on sampling time points of channels, and sequentially operate the unit analog beamformers to perform beamforming according to a time-interleaving scheme.
摘要翻译：超声波诊断装置的模拟波束成形器包括：分别分配给两个或更多个焦点的多个单位模拟波束形成器，并且被配置为通过换能器元件对从各个焦点接收到的信号进行波束成形并输出波束形成的信号; 模拟多路复用器，被配置为顺序地选择单位模拟波束形成器的输出信号并产生最终的输出信号; 时钟发生器，被配置为提供单位模拟波束形成器所需的时钟信号; 以及处理器，被配置为提供关于通道的采样时间点的信息，并且依次操作单位模拟波束形成器以根据时间交织方案执行波束成形。

4. 发明申请

US20100074095A1 TRANSMITTER CIRCUIT TO COMPENSATE FOR INFLUENCE OF CROSSTALK NOISE IN PRE-EMPHASIS SCHEME 失效
标题翻译：发射机电路，用于补偿CROSTALK噪声在预演方案中的影响
公开(公告)号：US20100074095A1
公开(公告)日：2010-03-25
申请号：US12512904
申请日：2009-07-30
申请人： Hae Kang JUNG , Hong June PARK , Kyoung Ho LEE
发明人： Hae Kang JUNG , Hong June PARK , Kyoung Ho LEE
IPC分类号： H04B3/21
CPC分类号： H04L25/03343 , H04L2025/03426
摘要： A transmitter circuit for transmitting parallel data, suitable for compensating for influence of crosstalk noise in a pre-emphasis scheme. The transmitter circuit includes first through Nth transmission lines configured to respectively transmit first through Nth data (N is 2 or greater); first through Nth output driving circuit sections configured to output the first through Nth data transmitted through the first through Nth transmission lines; first through Nth pre-emphasis circuit sections configured to generate first through Nth pre-emphasis signals for controlling transition output levels of the first through Nth data depending upon signal modes of adjoining data among the first through Nth data; and first through Nth adders configured to generate first through Nth data output signals that are controlled in transition output levels using output signals of the first through Nth output driving circuit sections and the first through Nth pre-emphasis signals.
摘要翻译：一种用于发送并行数据的发射机电路，适用于在预加重方案中补偿串扰噪声的影响。发射机电路包括分别发送第一至第N数据（N为2或更大）的第一至第N传输线。第一至第N输出驱动电路部分，被配置为输出通过第一至第N传输线传输的第一至第N数据; 第一至第N预加重电路部分，被配置为产生第一至第N预加重信号，用于根据第一至第N数据中相邻数据的信号模式来控制第一至第N数据的转换输出电平; 以及第一至第N加法器，被配置为使用第一至第N输出驱动电路部分的输出信号和第一至第N预加重信号产生以转换输出电平控制的第一至第N数据输出信号。

5. 发明申请

US20100283511A1 LOW POWER CONSUMPTION LOW KICK-BACK NOISE COMPARATOR CIRCUIT FOR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：低功耗低ICK K K NO E E TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER TER
公开(公告)号：US20100283511A1
公开(公告)日：2010-11-11
申请号：US12773537
申请日：2010-05-04
申请人： Jun Hyun BAE , Hong June PARK
发明人： Jun Hyun BAE , Hong June PARK
IPC分类号： H03K5/153
CPC分类号： H03K3/356139
摘要： The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.
摘要翻译：本发明涉及一种在模数转换器中使用的比较器电路，更具体地说，涉及用于模数转换器的低功耗低反冲噪声比较器电路，由于在信号比较操作中采用的信号再生方法在信号输入级中产生的背噪声，并且可以有效地降低功耗。

6. 发明申请

US20070170967A1 MULTI-PHASE CLOCK GENERATOR 失效
标题翻译：多相时钟发生器
公开(公告)号：US20070170967A1
公开(公告)日：2007-07-26
申请号：US11625541
申请日：2007-01-22
申请人： Seung Jun BAE , Hong June PARK
发明人： Seung Jun BAE , Hong June PARK
IPC分类号： H03K5/13
CPC分类号： H03K5/15013 , H03K5/1565 , H03K2005/00286 , H03L7/0814
摘要： Provided is a multi-phase clock generator which is not influenced by a mismatch and of which a maximum frequency is not limited. The multi-phase clock generator includes a first delay line, a second delay line, a phase detector, and an up/down counter. The first delay line generates a first clock signal by delaying an input clock for a first delay time. The second delay line generates a second clock signal by delaying the input clock for a second delay time in response to a control signal. The phase detector detects a phase difference between the first and second clock signals. The up/down counter generates the control signal in response to an output of the phase detector.
摘要翻译：提供了不受不匹配影响并且不限制最大频率的多相时钟发生器。多相时钟发生器包括第一延迟线，第二延迟线，相位检测器和上/下计数器。第一延迟线通过将输入时钟延迟第一延迟时间来产生第一时钟信号。第二延迟线响应于控制信号，通过将输入时钟延迟第二延迟时间来产生第二时钟信号。相位检测器检测第一和第二时钟信号之间的相位差。上/下计数器响应于相位检测器的输出而产生控制信号。

7. 发明申请

US20100284489A1 DIGITAL DIFFERENTIAL SIGNAL TRANSMITTER FOR LOW SUPPLY VOLTAGE 失效
标题翻译：用于低电压的数字差分信号发生器
公开(公告)号：US20100284489A1
公开(公告)日：2010-11-11
申请号：US12503048
申请日：2009-07-14
申请人： Jun Hyun BAE , Hong June PARK
发明人： Jun Hyun BAE , Hong June PARK
IPC分类号： H04L25/03
CPC分类号： H04L25/085 , H04J3/0685 , H04L7/0091 , H04L25/0272 , H04L25/0278
摘要： A digital differential signal transmitter circuit for a low supply voltage. A phase correction circuit for correcting digital signals transmitted through two signal paths in such a way as to have a phase relationship of differential signals and duty cycle correction circuits for correcting the digital signals in such a way as to maintain signal integrity in spite of changes in process, supply voltage and temperature are installed on the two signal paths so that the distortion of digital differential signals is compensated for. Power consumption at a final output section of the transmitter circuit is reduced. Impedances of the transmitter circuit and transmission lines are matched so that the transmitter circuit can operate insensitively with respect to operation circumstances.
摘要翻译：用于低电源电压的数字差分信号发射电路。一种相位校正电路，用于校正通过两个信号路径发送的数字信号，以便具有用于校正数字信号的差分信号和占空比校正电路的相位关系，以便尽可能保持信号完整性过程，电源电压和温度安装在两个信号路径上，以便数字差分信号的失真得到补偿。发射机电路最终输出部分的功耗降低。发射机电路和传输线路的阻抗匹配，使得发射机电路相对于操作环境不灵敏地操作。

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