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1. 发明申请

US20120034749A1 METHOD FOR MANUFACTURING A STRAINED SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造应变半导体器件的方法
公开(公告)号：US20120034749A1
公开(公告)日：2012-02-09
申请号：US13197658
申请日：2011-08-03
申请人： Kwan-Yong LIM , Chung-Geun Koh , Hyun-Jung Lee , Tae-Ouk Kwon , Seok-Hoon Kim , Tae-Ho Cha
发明人： Kwan-Yong LIM , Chung-Geun Koh , Hyun-Jung Lee , Tae-Ouk Kwon , Seok-Hoon Kim , Tae-Ho Cha
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/823807 , H01L29/7833 , H01L29/7843 , H01L29/7847
摘要： A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.
摘要翻译：可以通过在衬底上形成栅极结构并在栅极结构和衬底上形成扩散阻挡层来提供制造半导体器件的方法.A应力层可以形成在包含金属氮化物或金属的扩散阻挡层上具有与其相关联的氮或氧浓度的氧化物。应力层可以被加热以将应力层转变成拉伸应力层，以减小应力层中的氮或氧的浓度。可以去除拉伸应力层和扩散阻挡层。

2. 发明申请

US20060246669A1 Method for fabricating semiconductor devices having dual gate oxide layer 有权
公开(公告)号：US20060246669A1
公开(公告)日：2006-11-02
申请号：US11477090
申请日：2006-06-28
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

3. 发明授权

US07528042B2 Method for fabricating semiconductor devices having dual gate oxide layer 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07528042B2
公开(公告)日：2009-05-05
申请号：US11477090
申请日：2006-06-28
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅衬底没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

4. 发明授权

US07157339B2 Method for fabricating semiconductor devices having dual gate oxide layers 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07157339B2
公开(公告)日：2007-01-02
申请号：US10292296
申请日：2002-11-12
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅基板没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

5. 发明申请

US20110171818A1 METHODS OF FORMING A GATE STRUCTURE 有权
标题翻译：形成门结构的方法
公开(公告)号：US20110171818A1
公开(公告)日：2011-07-14
申请号：US13053923
申请日：2011-03-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern.
摘要翻译：可以通过在衬底上形成隧道绝缘层并在隧道绝缘层上形成浮栅来提供形成栅极结构的方法。电介质层图案可以在浮动栅极上，并且可以在介电层图案上形成控制栅极，其可以通过在电介质层图案上形成第一导电层图案来提供。可以在第一导电层图案上形成金属欧姆层图案。可以在金属欧姆层图案上形成扩散防止层图案。可以在形成非晶层图案上的第二导电层图案的扩散防止层图案上形成非晶层图案。可以通过在隧道绝缘层上形成附加的第一导电层图案来进一步形成浮栅。另外的金属欧姆层图案可以形成在附加的第一导电层图案上。附加的扩散防止层可以在附加金属欧姆层图案上形成图案。可以在附加的防扩散层图案上形成附加的非晶层图案，并且可以在附加的非晶层图案上形成附加的第二导电层图案。

6. 发明授权

US07989892B2 Gate structure, and semiconductor device having a gate structure 有权
标题翻译：栅极结构和具有栅极结构的半导体器件
公开(公告)号：US07989892B2
公开(公告)日：2011-08-02
申请号：US12483761
申请日：2009-06-12
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Jong-Min Baek , Jae-Hwa Park , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Hee-Sook Park
IPC分类号： H01L21/44
CPC分类号： H01L29/4933 , H01L21/28061 , H01L27/10873
摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer.
摘要翻译：栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模。

7. 发明申请

US20080121983A1 Gate and method of forming the same, and memory device and method of manufacturing the same 审中-公开
标题翻译：门及其形成方法，以及存储器件及其制造方法
公开(公告)号：US20080121983A1
公开(公告)日：2008-05-29
申请号：US11606899
申请日：2006-12-01
申请人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
发明人： Geum-Jung Seong , Gil-Heyun Choi , Byung-Hee Kim , Tae-Ho Cha , Hee-Sook Park , Jang-Hee Lee
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/40117 , H01L29/4234
摘要： A gate of a memory device may include a charge trapping structure having a tunnel oxide layer, a charge storing layer, and a blocking layer on a semiconductor substrate; a conductive pattern on the charge trapping structure, the conductive pattern including metal nitride; an ohmic film on the conductive pattern; and a gate electrode on the ohmic film.
摘要翻译：存储器件的栅极可以包括在半导体衬底上具有隧道氧化物层，电荷存储层和阻挡层的电荷俘获结构; 电荷捕获结构上的导电图案，导电图案包括金属氮化物; 导电图案上的欧姆膜; 和欧姆膜上的栅电极。

8. 发明授权

US07928498B2 Gate structures in semiconductor devices 有权
标题翻译：半导体器件中的栅极结构
公开(公告)号：US07928498B2
公开(公告)日：2011-04-19
申请号：US12428303
申请日：2009-04-22
申请人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
发明人： Tae-Ho Cha , Seong-Hwee Cheong , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jong-Min Baek
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L21/28282 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
摘要翻译：栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散防止层图案，扩散防止层图案和非晶层图案上的第二导电层图案。栅极结构可以具有低的薄层电阻和期望的热稳定性。

9. 发明授权

US07879737B2 Methods for fabricating improved gate dielectrics 有权
标题翻译：制造改进的栅极电介质的方法
公开(公告)号：US07879737B2
公开(公告)日：2011-02-01
申请号：US12801115
申请日：2010-05-24
申请人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
发明人： Woong-Hee Sohn , Gil-Heyun Choi , Byung-Hee Kim , Byung-Hak Lee , Tae-Ho Cha , Hee-Sook Park , Jae-Hwa Park , Geum-Jung Seong
IPC分类号： H01L21/31
CPC分类号： H01L21/823481 , H01L21/28202 , H01L21/28211 , H01L21/2822 , H01L29/518 , H01L29/66545 , H01L29/78 , Y10S438/981
摘要： Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.
摘要翻译：公开了用于增加栅极电介质图案的外围或边缘区域中的相对厚度以抑制这些区域的泄漏的各种方法。这些方法提供了常规GPOX工艺的替代方案，并提供改进的耐漏电性，而不会导致与GPOX工艺相关的增加的栅电极电阻的程度。每种方法包括形成第一开口以暴露有源区域区域，在暴露部分上形成氧化控制区域，然后形成第二开口，由此暴露氧化控制区域的外围区域以形成栅极介电层。得到的栅极介电层的特征在于由较厚的外围区域包围或界定的较薄的中心区域。

10. 发明授权

US07585787B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07585787B2
公开(公告)日：2009-09-08
申请号：US11648595
申请日：2007-01-03
申请人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
发明人： Tae-Ho Cha , Gil-Heyun Choi , Byung-Hee Kim , Hee-Sook Park , Jang-Hee Lee , Geum-Jung Seong
IPC分类号： H01L21/469
CPC分类号： H01L29/4941 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11568 , H01L29/513
摘要： A semiconductor memory device, e.g., a charge trapping type non-volatile memory device, may include a charge trapping structure formed in a first area of a substrate and a gate structure formed in a second area of the substrate. The charge trapping structure may include a tunnel oxide layer pattern, a charge trapping layer pattern and a dielectric layer pattern of aluminum-containing tertiary metal oxide. The gate structure may include a gate oxide layer pattern, a polysilicon layer pattern and an ohmic layer pattern of aluminum-containing tertiary metal silicide. A first electrode and a second electrode may be formed on the charge trapping structure. A lower electrode and an upper electrode may be provided on the gate structure. The dielectric layer pattern may have a higher dielectric constant, and the ohmic layer pattern may have improved thermal stability, thereby enhancing programming and erasing operations of the charge trapping type non-volatile memory device.
摘要翻译：半导体存储器件，例如电荷俘获型非易失性存储器件，可以包括形成在衬底的第一区域中的电荷俘获结构和形成在衬底的第二区域中的栅极结构。电荷捕获结构可以包括隧道氧化物层图案，电荷俘获层图案和含铝三级金属氧化物的介电层图案。栅极结构可以包括栅极氧化物层图案，多晶硅层图案和含铝三次金属硅化物的欧姆层图案。第一电极和第二电极可以形成在电荷捕获结构上。可以在栅极结构上设置下电极和上电极。电介质层图案可以具有更高的介电常数，并且欧姆层图案可以具有改善的热稳定性，从而增强电荷俘获型非易失性存储器件的编程和擦除操作。

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