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1. 发明申请

US20070185951A1 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US20070185951A1
公开(公告)日：2007-08-09
申请号：US11447329
申请日：2006-06-05
申请人： Kwan Yee Martin Lee , Martin Langhammer , Yi-Wen Lin , Triet M. Nguyen
发明人： Kwan Yee Martin Lee , Martin Langhammer , Yi-Wen Lin , Triet M. Nguyen
IPC分类号： G06F7/00
CPC分类号： G06F7/49963 , G06F7/49921 , G06F7/49947 , G06F7/5443
摘要： A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.
摘要翻译：用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路，以及用于对结果进行舍入的电路。四舍五入电路可以选择性地执行圆到最近和从最接近平移的操作。此外，优选地可选择进行舍入的位位置。专门的处理块优选地还包括用于防止溢出和下溢的饱和电路，并且优选地可选择饱和发生的位位置。舍入和饱和位置的选择性提供了输出数据字宽度的控制。舍入和饱和电路可以基于定时需要可选地位于不同的位置。类似地，可以使用前瞻模式来加速舍入，其中舍入和未包围的结果被并行计算，舍入逻辑在这些结果之间进行选择。

2. 发明授权

US08301681B1 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US08301681B1
公开(公告)日：2012-10-30
申请号：US11447474
申请日：2006-06-05
申请人： Kwan Yee Martin Lee , Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
发明人： Kwan Yee Martin Lee , Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00
CPC分类号： G06F7/483 , G06F7/4876 , G06F7/5443 , G06F2207/3884 , H03K19/17732
摘要： A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for performing floating point operations. The floating point circuitry preferably includes rounding and normalization circuitry. To perform mantissa multiplications, the floating point circuitry preferably relies on the aforementioned multipliers of the specialized processing block.
摘要翻译：用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路，以及用于执行浮点运算的电路。浮点电路优选地包括舍入和归一化电路。为了执行尾数乘法，浮点电路优选地依赖于上述专用处理块的乘法器。

3. 发明授权

US08266198B2 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US08266198B2
公开(公告)日：2012-09-11
申请号：US11447329
申请日：2006-06-05
申请人： Kwan Yee Martin Lee , Martin Langhammer , Yi-Wen Lin , Triet M. Nguyen
发明人： Kwan Yee Martin Lee , Martin Langhammer , Yi-Wen Lin , Triet M. Nguyen
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177
CPC分类号： G06F7/49963 , G06F7/49921 , G06F7/49947 , G06F7/5443
摘要： A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.
摘要翻译：用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路，以及用于对结果进行舍入的电路。四舍五入电路可以选择性地执行圆到最近和从最接近平移的操作。此外，优选地可选择进行舍入的位位置。专门的处理块优选地还包括用于防止溢出和下溢的饱和电路，并且优选地可选择饱和发生的位位置。舍入和饱和位置的选择性提供了输出数据字宽度的控制。舍入和饱和电路可以基于定时需要可选地位于不同的位置。类似地，可以使用前瞻模式来加速舍入，其中舍入和未包围的结果被并行计算，舍入逻辑在这些结果之间进行选择。

4. 发明授权

US07836117B1 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US07836117B1
公开(公告)日：2010-11-16
申请号：US11458361
申请日：2006-07-18
申请人： Martin Langhammer , Kwan Yee Martin Lee , Triet M. Nguyen , Keone Streicher , Orang Azgomi
发明人： Martin Langhammer , Kwan Yee Martin Lee , Triet M. Nguyen , Keone Streicher , Orang Azgomi
IPC分类号： G06F7/38
CPC分类号： G06F7/5324 , G06F5/01 , G06F7/4812 , G06F7/49921 , G06F7/49963 , G06F7/5443 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/1737
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译：用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。

5. 发明申请

US20070185952A1 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US20070185952A1
公开(公告)日：2007-08-09
申请号：US11447472
申请日：2006-06-05
申请人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Yi-Wen Lin
发明人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Yi-Wen Lin
IPC分类号： G06F7/00
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译：用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。

6. 发明授权

US08266199B2 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US08266199B2
公开(公告)日：2012-09-11
申请号：US11447472
申请日：2006-06-05
申请人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Yi-Wen Lin
发明人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Yi-Wen Lin
IPC分类号： G06F7/38
CPC分类号： H03K19/17732 , G06F7/527 , G06F7/5272
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.
摘要翻译：用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作。

7. 发明授权

US07822799B1 Adder-rounder circuitry for specialized processing block in programmable logic device 有权
标题翻译：用于可编程逻辑器件中专用处理块的加法器电路
公开(公告)号：US07822799B1
公开(公告)日：2010-10-26
申请号：US11426403
申请日：2006-06-26
申请人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
发明人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
IPC分类号： G06F7/38
CPC分类号： G06F7/509 , G06F7/49963 , G06F7/5016 , G06F7/508
摘要： Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.
摘要翻译：用于可编程逻辑器件的加法器/圆形电路可以快速计算舍入的并且理想地在一个时钟周期内计算。舍入位置可在位位置范围内选择。在输入级中，对于该范围内的每个位位置，处理来自两个加数和舍入位的位，而对于该范围之外的每个位位置，只处理来自两个加数的位。输入级处理以范围内和外的位的通用格式对齐其输出。输入处理可以包括在该范围内的比特位置的3：2压缩，以及在该范围之外的比特位置的2：2压缩，使得对和矢量和进位向量的所有比特位置执行进一步的处理。总和的计算基本上与舍入输入同时进行，并且舍入逻辑在计算中稍后进行选择。

8. 发明授权

US08041759B1 Specialized processing block for programmable logic device 有权
标题翻译：可编程逻辑器件专用处理块
公开(公告)号：US08041759B1
公开(公告)日：2011-10-18
申请号：US11447370
申请日：2006-06-05
申请人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Robert L. Pelt
发明人： Martin Langhammer , Kwan Yee Martin Lee , Orang Azgomi , Keone Streicher , Robert L. Pelt
IPC分类号： H03K19/173 , H01L25/00 , G06F17/10 , G06F17/17 , G06F7/38
CPC分类号： H03K19/177
摘要： A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.
摘要翻译：用于可编程逻辑器件的专用处理块包括执行两次乘法和的基本处理单元，将两个乘法的部分乘积相加，而不计算各个乘法。这种基本处理单元消耗的面积小于传统的单独乘法器和加法器。专用处理块还具有输入和输出级以及环回功能，以允许块被配置用于各种数字信号处理操作，包括有限脉冲响应（FIR）滤波器和无限脉冲响应（IIR）滤波器。通过使用可编程连接，在某些情况下可编程逻辑器件的可编程资源，以及以比可编程逻辑器件的其余部分更高的时钟速度运行专用处理器的部分，可以实现更复杂的FIR和IIR滤波器。

9. 发明授权

US08856201B1 Mixed-mode multiplier using hard and soft logic circuitry 有权
标题翻译：使用硬和软逻辑电路的混合模式乘法器
公开(公告)号：US08856201B1
公开(公告)日：2014-10-07
申请号：US13447687
申请日：2012-04-16
申请人： Martin Langhammer , Kwan Yee Martin Lee , Ali H. Burney
发明人： Martin Langhammer , Kwan Yee Martin Lee , Ali H. Burney
IPC分类号： G06F7/523
CPC分类号： G06F7/5318 , H03K19/17732 , H03K19/17736
摘要： Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.
摘要翻译：提供了有效利用可编程逻辑器件（PLD）的硬和软逻辑区域的乘法器电路。乘法器电路包括部分乘积生成块，压缩块（例如，进位保存加法器）和进位传播加法器级。部分乘积生成和压缩块在硬逻辑中实现，而进位传播加法器以软逻辑实现。本地或全局路由可用于连接硬和软乘法器组件。乘法器还可以包括硬逻辑中的可选输入寄存器和/或软逻辑中的可选输出寄存器。这种混合模式设计可以大大节省实现乘法器所需的硬逻辑量，而不会显着降低乘法器性能。

10. 发明授权

US08805916B2 Digital signal processing circuitry with redundancy and bidirectional data paths 有权
标题翻译：具有冗余和双向数据路径的数字信号处理电路
公开(公告)号：US08805916B2
公开(公告)日：2014-08-12
申请号：US12380841
申请日：2009-03-03
申请人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
发明人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00 , H03K19/173 , H03K19/177 , H01L25/00 , H03K5/1252 , G06F7/53
CPC分类号： H03K5/1252 , G06F7/5324 , G06F2207/382 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。

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