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1. 发明授权

US07084664B1 Integrated circuits with reduced interconnect overhead 失效
标题翻译：具有减少互连开销的集成电路
公开(公告)号：US07084664B1
公开(公告)日：2006-08-01
申请号：US10867456
申请日：2004-06-14
申请人： Kwan Yee Lee , Martin Langhammer , Ali H. Burney
发明人： Kwan Yee Lee , Martin Langhammer , Ali H. Burney
IPC分类号： G06F7/38 , H03K19/173 , H04Q7/00 , H04Q7/28
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17784
摘要： Integrated circuits are provided that use on-chip data compression and decompression to minimize consumption of interconnect resources. Parallel-to-serial converter circuitry can use time-division multiplexing techniques to compress data. The compressed data may be conveyed between circuit blocks on the integrated circuit using a reduced number of parallel interconnect conductors. After the compressed data has been conveyed to its destination, a serial-to-parallel converter may use time-division demultiplexing techniques to decompress the data. Interconnect resources may be shared by dedicated circuits. With this arrangement, signals can be selectively steered through the appropriate dedicated circuitry to either maximize performance or to use compression and decompression to minimize interconnect resource consumption.
摘要翻译：提供了使用片上数据压缩和解压缩以最小化互连资源消耗的集成电路。并行到串行转换器电路可以使用时分复用技术来压缩数据。压缩数据可以使用减少数量的并联互连导体在集成电路上的电路块之间传送。在将压缩数据传送到其目的地之后，串行到并行转换器可以使用时分解复用技术来解压缩数据。互连资源可以由专用电路共享。通过这种安排，可以通过适当的专用电路选择性地控制信号，以最大化性能或使用压缩和解压缩来最小化互连资源消耗。

2. 发明授权

US07282973B1 Enhanced DLL phase output scheme 有权
标题翻译：增强的DLL相输出方案
公开(公告)号：US07282973B1
公开(公告)日：2007-10-16
申请号：US11297040
申请日：2005-12-07
申请人： Sanjay K. Charagulla , Ali H. Burney
发明人： Sanjay K. Charagulla , Ali H. Burney
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0814 , H03L7/0818
摘要： A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.
摘要翻译：公开了一种使用延迟锁定环（DLL）以离散相位间隔提供多个锁相输出的方法和系统。在一个实施例中，参考时钟信号通过具有多个延迟元件的延迟链传输。延迟链能够从参考时钟信号产生多个输出时钟信号。每个输出时钟信号相对于延迟元件以离散相移间隔被延迟。输出时钟信号和参考时钟信号中的第一个耦合到能够与延迟链形成第一DLL的第一相位比较器。输出时钟信号和参考时钟信号中的第二个耦合到能够与延迟链形成第二DLL的第二相位比较器。可以以编程方式选择来自第一DLL或第二DLL的输出时钟信号。

3. 发明授权

US07257655B1 Embedded PCI-Express implementation 有权
标题翻译：嵌入式PCI-Express实现
公开(公告)号：US07257655B1
公开(公告)日：2007-08-14
申请号：US10964979
申请日：2004-10-13
申请人： Ali H. Burney , Sanjay Charagulla , Daniel Mansur
发明人： Ali H. Burney , Sanjay Charagulla , Daniel Mansur
IPC分类号： G06F13/42 , G06F12/00 , H04K1/00
CPC分类号： G06F13/423
摘要： Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.
摘要翻译：方法和设备在可编程设备上提供PCI Express支持。一种设备包括硬编码收发器，其支持与PCI Express物理层和链路层相关联的功能。硬编码收发器还可以支持部分PCI Express事务层。软编码逻辑用于支持更高层功能，包括事务层的一部分，以允许自定义配置PCI Express功能，如虚拟通道，缓冲区，优先级和服务质量特性。混合解决方案降低了逻辑资源成本，并提供了有效的定制可配置解决方案。

4. 发明授权

US07343388B1 Implementing crossbars and barrel shifters using multiplier-accumulator blocks 有权
标题翻译：使用乘法器累加器块实现十字路口和桶形移位器
公开(公告)号：US07343388B1
公开(公告)日：2008-03-11
申请号：US10383304
申请日：2003-03-05
申请人： Ali H Burney , Guy R Schlacter
发明人： Ali H Burney , Guy R Schlacter
IPC分类号： G06F15/00
CPC分类号： G06F5/01 , G06F7/5443
摘要： An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burst of data and writes the data into a larger data column where the data is barrel-shifted using multiplier-accumulator blocks and transferred out of the receiver when an end-of-packet is detected or the shifted data column as seen from outside the interface receiver is full.
摘要翻译：接口接收器是允许在两个不兼容的I / O标准之间传输数据的接口的一部分，包括可以使用乘法器累加器块实现的交叉开关和桶形移位器。交叉开关重新排序输入的数据突发，并将数据写入更大的数据列，其中使用乘法器累加器块对数据进行桶形移位，并且当检测到分组结束时将其从接收器传送出去，或者将移位的数据列作为从界面接收器外面看到的是满的。

5. 发明授权

US07057412B1 Configurable crossbar switch 失效
标题翻译：可配置的交叉开关
公开(公告)号：US07057412B1
公开(公告)日：2006-06-06
申请号：US10734474
申请日：2003-12-12
申请人： Ali H Burney
发明人： Ali H Burney
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17772 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17752 , H03K19/17756
摘要： A configurable crossbar switch is provided between the signaling I/O and the IP block in a programmable logic resource. A programmable logic resource receives input data via an I/O port. This data is decoded in an I/O buffer and sent as input to a crossbar switch that can be configured to send the data to any one of the data ports in the IP block. Similarly, data from the IP block can be sent via a data port to a crossbar switch that can be configured to send the data to an I/O buffer that encodes the data for output to any one of the I/O ports. The use of crossbar switch provides greater flexibility in the design of a programmable logic resource and reduces connectivity problems.
摘要翻译：在可编程逻辑资源中，在信令I / O和IP块之间提供可配置的交叉开关。可编程逻辑资源通过I / O端口接收输入数据。该数据在I / O缓冲器中被解码并作为输入发送到可被配置为将数据发送到IP块中的任何一个数据端口的交叉开关。类似地，来自IP块的数据可以通过数据端口发送到交叉开关，交叉开关可配置为将数据发送到I / O缓冲器，该I / O缓冲器编码数据以输出到任何一个I / O端口。使用交叉开关在可编程逻辑资源的设计中提供更大的灵活性，并减少连接问题。

6. 发明授权

US07696781B1 Methods and apparatus for control and configuration of programmable logic devices 失效
标题翻译：用于控制和配置可编程逻辑器件的方法和装置
公开(公告)号：US07696781B1
公开(公告)日：2010-04-13
申请号：US12291923
申请日：2008-11-14
申请人： Ali H. Burney , Daniel R. Mansur
发明人： Ali H. Burney , Daniel R. Mansur
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17732
摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.
摘要翻译：提供电路和方法来控制和配置PLD。本发明的实施例包括嵌入在PLD中的硬IP电路。电路可以包括千兆MAC，硬处理器和DMA引擎。本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

7. 发明授权

US07468613B1 Methods and apparatus for control and configuration of programmable logic devices 失效
标题翻译：用于控制和配置可编程逻辑器件的方法和装置
公开(公告)号：US07468613B1
公开(公告)日：2008-12-23
申请号：US11893722
申请日：2007-08-16
申请人： Ali H. Burney , Daniel R. Mansur
发明人： Ali H. Burney , Daniel R. Mansur
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17732
摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.
摘要翻译：提供电路和方法来控制和配置PLD。本发明的实施例包括嵌入在PLD中的硬IP电路。电路可以包括千兆MAC，硬处理器和DMA引擎。本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

8. 发明授权

US08856201B1 Mixed-mode multiplier using hard and soft logic circuitry 有权
标题翻译：使用硬和软逻辑电路的混合模式乘法器
公开(公告)号：US08856201B1
公开(公告)日：2014-10-07
申请号：US13447687
申请日：2012-04-16
申请人： Martin Langhammer , Kwan Yee Martin Lee , Ali H. Burney
发明人： Martin Langhammer , Kwan Yee Martin Lee , Ali H. Burney
IPC分类号： G06F7/523
CPC分类号： G06F7/5318 , H03K19/17732 , H03K19/17736
摘要： Multiplier circuitry that efficiently utilizes the hard and soft logic regions of a programmable logic device (PLD) is provided. The multiplier circuitry includes a partial product generation block, a compression block (e.g., a carry-save adder), and an carry-propagate adder stage. The partial product generation and compression block are implemented in hard logic while the carry-propagate adder is implemented in soft logic. Local or global routing may be used to connect the hard and soft multiplier components. The multiplier may further include a selectable input register in hard logic and/or a selectable output register in soft logic. This mixed-mode design allows for a substantial savings in the amount of hard logic required to implement the multiplier without a significant decrease in multiplier performance.
摘要翻译：提供了有效利用可编程逻辑器件（PLD）的硬和软逻辑区域的乘法器电路。乘法器电路包括部分乘积生成块，压缩块（例如，进位保存加法器）和进位传播加法器级。部分乘积生成和压缩块在硬逻辑中实现，而进位传播加法器以软逻辑实现。本地或全局路由可用于连接硬和软乘法器组件。乘法器还可以包括硬逻辑中的可选输入寄存器和/或软逻辑中的可选输出寄存器。这种混合模式设计可以大大节省实现乘法器所需的硬逻辑量，而不会显着降低乘法器性能。

9. 发明授权

US07274212B1 Methods and apparatus for control and configuration of programmable logic device 有权
标题翻译：用于可编程逻辑器件的控制和配置的方法和装置
公开(公告)号：US07274212B1
公开(公告)日：2007-09-25
申请号：US10980963
申请日：2004-11-04
申请人： Ali H Burney , Daniel R Mansur
发明人： Ali H Burney , Daniel R Mansur
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/17732
摘要： Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of operations, including real-time control and remote programming, without the use of dedicated external circuitry.
摘要翻译：提供电路和方法来控制和配置PLD。本发明的实施例包括嵌入在PLD中的硬IP电路。电路可以包括千兆MAC，硬处理器和DMA引擎。本发明允许多种操作，包括实时控制和远程编程，而不使用专用的外部电路。

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