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1. 发明授权

US6057189A Method of fabricating capacitor utilizing an ion implantation method 失效
标题翻译：使用离子注入法制造电容器的方法
公开(公告)号：US6057189A
公开(公告)日：2000-05-02
申请号：US24183
申请日：1998-02-17
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Wen-Kuan Yeh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Wen-Kuan Yeh , Tri-Rung Yew
IPC分类号： H01L27/04 , H01L21/02 , H01L21/28 , H01L21/314 , H01L21/822 , H01L21/8242
CPC分类号： H01L28/40 , Y10S438/964
摘要： A method of fabricating a capacitor, comprising the steps of: providing a conductive layer over a semiconductor substrate having a transistor formed thereon to connect a source/drain region of the transistor; forming a hemispherical grained silicon layer over the conductive layer; using an implantation method to implant ions into the hemispherical grained silicon layer; performing a thermal treatment process to convert the ions into a barrier layer over the hemispherical grained silicon layer; performing a wet etching process to clean a surface of the barrier layer; forming a dielectric layer over the barrier layer and forming a top electrode over the dielectric layer.
摘要翻译：一种制造电容器的方法，包括以下步骤：在其上形成有晶体管的半导体衬底上提供导电层以连接晶体管的源极/漏极区域; 在所述导电层上形成半球形晶粒硅层; 使用植入方法将离子注入到半球形晶粒硅层中; 执行热处理工艺以将离子转换成半球形晶粒硅层上的阻挡层; 执行湿蚀刻工艺以清洁阻挡层的表面; 在阻挡层上形成电介质层，并在电介质层上形成顶部电极。

2. 发明授权

US06479344B2 Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US06479344B2
公开(公告)日：2002-11-12
申请号：US09542715
申请日：2000-04-04
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3211 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.
摘要翻译：制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。电容器的结构简单，易于执行。此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

3. 发明授权

US06403411B1 Method for manufacturing lower electrode of DRAM capacitor 失效
标题翻译：制造DRAM电容器下电极的方法
公开(公告)号：US06403411B1
公开(公告)日：2002-06-11
申请号：US09208601
申请日：1998-12-08
申请人： Chih-Hsun Chu , Horng-Nan Chern , Kevin Lin , Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Chih-Hsun Chu , Horng-Nan Chern , Kevin Lin , Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218234
CPC分类号： H01L28/84 , H01L21/76895
摘要： A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.
摘要翻译：一种用于制造DRAM电容器的下电极的方法。该方法包括沉积多晶硅而不是非晶硅以形成下电极。由于多晶硅具有较高的沉积温度，因此具有更高的沉积速率，能够缩短沉积时间。在形成多晶硅下电极之后，通过用离子轰击多晶硅层将多晶硅层的上部转变成非晶层，以破坏其内部结构。最终，半球形晶粒硅能够在下电极上生长，从而增加其表面积。

4. 发明授权

US06218238B1 Method of fabricating DRAM capacitor 有权
标题翻译：制造DRAM电容的方法
公开(公告)号：US06218238B1
公开(公告)日：2001-04-17
申请号：US09172458
申请日：1998-10-14
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3211 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.
摘要翻译：制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。电容器的结构简单，易于执行。此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

5. 发明授权

US6146941A Method for fabricating a capacitor in a semiconductor device 失效
标题翻译：在半导体器件中制造电容器的方法
公开(公告)号：US6146941A
公开(公告)日：2000-11-14
申请号：US128221
申请日：1998-08-03
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01L21/8244 , H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L27/10852 , H01L28/82
摘要： A fabricating method of a capacitor includes two gates and a commonly used source/drain region formed on a substrate. Then, a process of sell align contact has been applied to make a pitted self align contact window (PSACW) to partly expose the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are formed over the PSACW. Then a dielectric thin film with a material having high dielectric constant is formed over the lower electrode. Then, an upper electrode is formed over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.
摘要翻译：电容器的制造方法包括形成在基板上的两个栅极和常用的源极/漏极区域。然后，已经应用了销售对齐接触的过程，以形成凹陷的自对准接触窗口（PSACW）以部分地暴露常用的源极/漏极区域。然后在PSACW上形成电容器的胶/阻挡层和下电极。然后在下部电极上形成具有高介电常数的材料的电介质薄膜。然后，在电介质薄膜的上方形成上部电极，形成电容器，该电容器具有像PSACW的形状的金属绝缘体金属的结构。

6. 发明授权

US06078492A Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall 失效
标题翻译：具有具有倾斜侧壁的自对准接触窗的半导体器件中的电容器的结构
公开(公告)号：US06078492A
公开(公告)日：2000-06-20
申请号：US128364
申请日：1998-08-03
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01G4/30 , H01G4/008
CPC分类号： H01L27/10852 , H01L28/82
摘要： A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film with a material having high dielectric constant is over the lower electrode. Then, an upper electrode is over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.
摘要翻译：电容器的结构包括两个栅极和在衬底上的常用源极/漏极区域。然后，凹陷的自对准接触窗口（PSACW）部分地暴露常用的源极/漏极区域。然后电容器的胶/阻挡层和下电极在PSACW之上。然后，具有高介电常数的材料的电介质薄膜在下电极之上。然后，上电极在电介质薄膜的上方，以完成电容器，该电容器具有类似于PSACW形状的金属绝缘体金属的结构。

7. 发明授权

US6083789A Method for manufacturing DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US6083789A
公开(公告)日：2000-07-04
申请号：US60323
申请日：1998-04-14
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/91
摘要： A method for forming a DRAM capacitor whose titanium nitride electrode is fabricated in a sequence of steps that results in a good step-coverage. Moreover, contamination of the titanium nitride layer and cross-diffusion between the titanium nitride layer and the dielectric film layer is reduced to a minimum. The method of forming the titanium nitride layer includes the steps of depositing a first titanium nitride layer over a dielectric film layer using a conventional physical vapor deposition process. Then, a second titanium nitride layer is deposited over the first titanium nitride layer using a collimated physical vapor deposition process.
摘要翻译：一种形成DRAM电容器的方法，其中氮化钛电极以一系列步骤制造，这导致良好的阶梯覆盖。此外，氮化钛层的污染和氮化钛层与电介质膜层之间的交叉扩散减少到最小。形成氮化钛层的方法包括以下步骤：使用常规的物理气相沉积工艺在电介质膜层上沉积第一氮化钛层。然后，使用准直的物理气相沉积工艺在第一氮化钛层上沉积第二氮化钛层。

8. 发明授权

US5994183A Method for forming charge storage structure 失效
标题翻译：电荷储存结构形成方法
公开(公告)号：US5994183A
公开(公告)日：1999-11-30
申请号：US996696
申请日：1997-12-23
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/60 , H01L21/28518 , H01L27/10852
摘要： A method for forming a high capacitance charge storage structure that can be applied to a substrate wafer having MOS transistor already formed thereon. The method is to form an insulating layer above the substrate wafer. Next, a contact window exposing a source/drain region is formed in the insulating layer. Then, a tungsten suicide layer, which functions as a lower electrode for the charge storage structure, is formed over the substrate. Thereafter, a tungsten nitride layer is formed over the tungsten silicide layer, and then a dielectric layer is formed over the tungsten nitride layer. The dielectric layer is preferably a tantalum oxide layer. Finally, a titanium nitride layer, which functions as an upper electrode for the charge storage structure, is formed over the tantalum oxide layer.
摘要翻译：一种用于形成可以应用于已经形成有MOS晶体管的衬底晶片的高电容电荷存储结构的方法。该方法是在衬底晶片之上形成绝缘层。接下来，在绝缘层中形成暴露源极/漏极区域的接触窗口。然后，在基板上形成用作电荷存储结构的下电极的硅化钨层。此后，在硅化钨层之上形成氮化钨层，然后在氮化钨层上形成电介质层。电介质层优选为氧化钽层。最后，在钽氧化物层上形成用作电荷存储结构的上电极的氮化钛层。

9. 发明授权

US6080660A Via structure and method of manufacture 失效
标题翻译：通过结构和制造方法
公开(公告)号：US6080660A
公开(公告)日：2000-06-27
申请号：US32682
申请日：1998-02-27
申请人： Kun-Chih Wang , Hsiao-Pang Chou , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kun-Chih Wang , Hsiao-Pang Chou , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76805
摘要： A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.
摘要翻译：一种用于制造通孔结构的方法，包括以下步骤：提供半导体衬底，然后在衬底上形成导电线和电介质层。接下来，进行光刻和第一蚀刻操作，从而形成暴露导电线表面的电介质层中的开口。第一蚀刻操作使用多种蚀刻剂，包括具有最高浓度的氟代丁烷。由于在开口的底部存在再入口结构，因此进行第二蚀刻操作。在第二蚀刻操作中，导电线的一部分被蚀刻固定的时间间隔以控制蚀刻程度。因此，在开口的底部形成倾斜表面，并且消除了再入口结构。在平坦化的底部，随后沉积材料的阶梯覆盖率增加。

10. 发明授权

US5994181A Method for forming a DRAM cell electrode 失效
标题翻译：用于形成DRAM单元电极的方法
公开(公告)号：US5994181A
公开(公告)日：1999-11-30
申请号：US858398
申请日：1997-05-19
申请人： Wen-Yi Hsieh , Tri-Rung Yew
发明人： Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/60 , H01L28/82
摘要： A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next, photolithography and etching process are used to etch the doped polysilicon layer, and form a bottom electrode of DRAM cell capacitor with U shape in cross section view. The next step of the formation is the deposition of a dielectric film along the surface of the bottom electrode of DRAM cell capacitor. Typically, the dielectric film is preferably formed of high dielectric film such as tantalum oxide (Ta.sub.2 0.sub.5). A conductive layer is deposited over the dielectric film. The conductive layer is used as the top storage node and is formed of titanium nitride(TiN). The methods of forming the top storage node, including sputtered-TiN, collimated-sputtering TiN, and CVD/MOCVD-TiN deposition. The purposes of sputtered-TiN and collimated-sputtering TiN processes can improve the poor step coverage of deep well of bottom electrode of DRAM cell capacitor and protect the Ta.sub.2 0.sub.5 from C, Cl, F contamination during CVD/MOCVD-TiN deposition process.
摘要翻译：随后通过使用CVD将多晶硅层沉积在电介质层上。接下来，使用光刻和蚀刻工艺来蚀刻掺杂多晶硅层，并且在横截面图中形成具有U形的DRAM单元电容器的底部电极。形成的下一步是沿着DRAM单元电容器的底部电极的表面沉积电介质膜。通常，电介质膜优选由诸如氧化钽（Ta 2 O 5）的高介电膜形成。导电层沉积在电介质膜上。导电层用作顶部存储节点并且由氮化钛（TiN）形成。形成顶部存储节点的方法包括溅射TiN，准直溅射TiN和CVD / MOCVD-TiN沉积。溅射TiN和准直溅射TiN工艺的目的可以改善DRAM单元电容器底部电极深阱的差的覆盖范围，并在CVD / MOCVD-TiN沉积过程中保护Ta205不受C，Cl，F污染。

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