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1. 发明授权

US4844776A Method for making folded extended window field effect transistor 失效
标题翻译：折叠扩展窗场效应晶体管的方法
公开(公告)号：US4844776A
公开(公告)日：1989-07-04
申请号：US128834
申请日：1987-12-04
申请人： Kuo-Hua Lee , Chih-Yuan Lu , David S. Yaney
发明人： Kuo-Hua Lee , Chih-Yuan Lu , David S. Yaney
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76895
摘要： A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. The window pad layer may also be used as a sublevel interconnect.

2. 发明授权

US4922311A Folded extended window field effect transistor 失效
标题翻译：折叠扩展窗场效应晶体管
公开(公告)号：US4922311A
公开(公告)日：1990-05-01
申请号：US336197
申请日：1989-04-11
申请人： Kuo-Hua Lee , Chih-Yuan Lu , David S. Yaney
发明人： Kuo-Hua Lee , Chih-Yuan Lu , David S. Yaney
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76895 , Y10S257/90 , Y10S257/915
摘要： A gate electrode having an insulating top layer as well as insulating sidewall spacers permits the source and drain regions to be electrically contacted through windows directly above the source and drain regions formed in a window pad layer. There is a conducting layer, termed a window pad layer, over portions of these regions. Because of the insulating top layer and sidewall spacers on the gate, the window may be misaligned with respect to the source and drain regions, and maybe even closer to the gate than are these regions, but electrical contacts to these regions are still obtained. The window pad layer may also be used as sublevel interconnect.
摘要翻译：具有绝缘顶层以及绝缘侧壁间隔物的栅电极允许源区和漏区通过形成在窗垫层中的源区和漏区正上方的窗口电接触。在这些区域的一部分上存在称为窗垫层的导电层。由于栅极上的绝缘顶层和侧壁间隔物，窗口可能相对于源极和漏极区域不对准，并且可能甚至比这些区域更接近栅极，但仍然获得与这些区域的电接触。窗口垫层也可以用作子层互连。

3. 发明授权

US4952524A Semiconductor device manufacture including trench formation 失效
标题翻译：半导体器件制造包括沟槽形成
公开(公告)号：US4952524A
公开(公告)日：1990-08-28
申请号：US347975
申请日：1989-05-05
申请人： Kuo-Hua Lee , Chih-Yuan Lu
发明人： Kuo-Hua Lee , Chih-Yuan Lu
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/316 , H01L21/762
CPC分类号： H01L21/31604 , H01L21/31051 , H01L21/31055 , H01L21/76229
摘要： A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.

4. 发明授权

US5002898A Integrated-circuit device isolation 失效
标题翻译：集成电路器件隔离
公开(公告)号：US5002898A
公开(公告)日：1991-03-26
申请号：US423992
申请日：1989-10-19
申请人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Larry B. Fritzinger , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/76 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202
摘要： In the manufacture of integrated-circuit semiconductor devices, prior to formation of a field oxide, a mask structure is provided on a silicon device area, comprising a pad oxide layer, a polysilicon buffer layer, a protective oxide layer, and a silicon nitride mask layer. Inclusion of the protective layer between polysilicon and silicon nitride layers prevents pad oxide failure and attendant substrate etching during strip-etching of the structure overlying the pad oxide.

5. 发明授权

US4935376A Making silicide gate level runners 失效
标题翻译：制作硅化物浇口水平赛跑者
公开(公告)号：US4935376A
公开(公告)日：1990-06-19
申请号：US420207
申请日：1989-10-12
申请人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Steven J. Hillenius , Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76889 , H01L21/28052 , H01L21/28123
摘要： Integrated circuits are fabricated with thick self-aligned silicide runners on the field oxide by etching back the first dielectric to expose patterned polysilicon on the field oxide and then forming a silicide on the patterned polysilicon.

6. 发明授权

US5679589A FET with gate spacer 失效
标题翻译： FET带栅极间隔
公开(公告)号：US5679589A
公开(公告)日：1997-10-21
申请号：US866942
申请日：1992-04-03
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
摘要翻译：公开了一种半导体集成电路结构及其制造方法。该结构包括具有相邻的双层或三层栅极间隔物的FET栅极。间隔物允许精细地定制具有深浅接合部分的轻掺杂漏极结型材。此外，自对准硅化物可以仅形成在深结部分上方，从而产生与源极和漏极的可靠的低接触电阻连接。

7. 发明授权

US5153145A FET with gate spacer 失效
标题翻译：带栅极间隔的FET
公开(公告)号：US5153145A
公开(公告)日：1992-10-06
申请号：US422834
申请日：1989-10-17
申请人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
发明人： Kuo-Hua Lee , Chih-Yuan Lu , Janmye Sung
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66575 , H01L29/6656 , H01L29/6659 , H01L29/78
摘要： A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.

8. 发明授权

US08833136B2 Rotary-drum hydraulic-impact abrasion testing machine 有权
标题翻译：旋转鼓式液压冲击磨损试验机
公开(公告)号：US08833136B2
公开(公告)日：2014-09-16
申请号：US13529013
申请日：2012-06-21
申请人： Ta-Peng Chang , Chih-Yen Lin , Kuo-Hua Lee , Tzong-Ruey Yang
发明人： Ta-Peng Chang , Chih-Yen Lin , Kuo-Hua Lee , Tzong-Ruey Yang
IPC分类号： G01N3/56
CPC分类号： G01N3/56 , G01N3/567
摘要： The present invention relates to a rotary-drum hydraulic-impact abrasion testing machine, which is used to process an abrasion test and a damage simulation for a plurality of hydraulics structures and comprises: a rotary-drum supporting framework, a rotary-drum and a plurality of sample fixing assembly. The sample fixing assembly at least comprises a housing, a first spacer and a plurality of first studs. In which, there are a plurality of sample openings formed on the side wall of the rotary-drum for respectively accommodating the hydraulics structure samples, and each sample opening is disposed with a long blocking plate and a short blocking plate on the two sides thereof. In the present invention, the rotary-drum hydraulic-impact abrasion testing machine is used to simultaneously execute the abrasion test and the damage simulation for multi hydraulics structures precisely.
摘要翻译：本发明涉及一种用于处理多个液压结构的磨损试验和损伤模拟的旋转滚筒液压冲击磨损试验机，包括：旋转滚筒支撑框架，旋转滚筒和多个样品固定组件。样品固定组件至少包括壳体，第一间隔件和多个第一螺栓。其中，在旋转鼓的侧壁上形成有用于分别容纳液压结构样品的多个样品开口，并且每个样品开口在其两侧设置有长阻挡板和短阻挡板。在本发明中，旋转滚筒液压冲击磨损试验机用于精确地同时执行多液压结构的磨损试验和损伤模拟。

9. 发明申请

US20100171509A1 CHIP TESTING CIRCUIT 有权
标题翻译：芯片测试电路
公开(公告)号：US20100171509A1
公开(公告)日：2010-07-08
申请号：US12548828
申请日：2009-08-27
申请人： Der-Min YUAN , Ming-Cheng Liang , Kuo-Hua Lee
发明人： Der-Min YUAN , Ming-Cheng Liang , Kuo-Hua Lee
IPC分类号： G01R31/02
CPC分类号： G01R31/31921 , G11C29/40
摘要： The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.
摘要翻译：本发明公开了一种提高测试吞吐量的芯片测试电路。芯片测试电路使用多路复用器在数据压缩基础单元之间切换数据压缩电路的连接，压缩基站单元压缩4个XIO，以便通过单个接口电路获得测试数据的多路复用器，并提高测试吞吐量。

10. 发明授权

US5956618A Process for producing multi-level metallization in an integrated circuit 失效
标题翻译：在集成电路中生产多级金属化的工艺
公开(公告)号：US5956618A
公开(公告)日：1999-09-21
申请号：US828155
申请日：1997-03-27
申请人： Chun-Ting Liu , Kuo-Hua Lee , Ruichen Liu
发明人： Chun-Ting Liu , Kuo-Hua Lee , Ruichen Liu
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/027 , H01L21/304
CPC分类号： H01L21/76838 , Y10S438/942
摘要： A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.
摘要翻译：公开了一种用于制造多电平集成电路的方法，其利用网格图案，从其中选择性地去除与金属层相对应的部分以形成掩模，其随后用于在金属线之间的开放区域中沉积虚拟特征，从而允许在金属层和虚拟特征上沉积基本上平面的电介质表面。

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