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1. 发明申请

US20080116496A1 Integrating a DRAM with an SRAM having butted contacts and resulting devices 审中-公开
标题翻译：将DRAM与具有对接触点和所产生的器件的SRAM集成
公开(公告)号：US20080116496A1
公开(公告)日：2008-05-22
申请号：US11809642
申请日：2007-06-01
申请人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
发明人： Kuo-Chyuan Tzeng , Kuo-Chiang Ting , Chen-Jong Wang , Min-Hsiung Chiang , Chih-Yang Pai
IPC分类号： H01L27/108
CPC分类号： H01L27/105 , H01L27/10894 , H01L27/11 , H01L27/1116
摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.
摘要翻译：提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

2. 发明授权

US07208369B2 Dual poly layer and method of manufacture 有权
标题翻译：双层多层及其制造方法
公开(公告)号：US07208369B2
公开(公告)日：2007-04-24
申请号：US10662609
申请日：2003-09-15
申请人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
发明人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
IPC分类号： H01L21/8242
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , Y10S257/903 , Y10S257/904
摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.
摘要翻译：提供了具有双重多晶硅电极的半导体器件和制造方法。半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。每个多晶硅层可以单独掺杂。该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

3. 发明申请

US20050056885A1 Dual poly layer and method of manufacture 有权
标题翻译：双层多层及其制造方法
公开(公告)号：US20050056885A1
公开(公告)日：2005-03-17
申请号：US10662609
申请日：2003-09-15
申请人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
发明人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/76
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , Y10S257/903 , Y10S257/904
摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.
摘要翻译：提供了具有双重多晶硅电极的半导体器件和制造方法。半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。每个多晶硅层可以单独掺杂。该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

4. 发明授权

US06383863B1 Approach to integrate salicide gate for embedded DRAM devices 有权
标题翻译：为嵌入式DRAM设备集成自杀门的方法
公开(公告)号：US06383863B1
公开(公告)日：2002-05-07
申请号：US09963595
申请日：2001-09-27
申请人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Hsiao-Hui Tseng , Hsien-Yuan Chang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/76889 , H01L21/76897 , H01L27/10873 , H01L27/10888 , H01L28/84 , H01L28/90 , H01L29/66545
摘要： A process for integrating the formation of a salicide layer on DRAM word line structures, and on a bit line contact structure, has been developed. The process features selective etch back of the insulator layers embedding the tapered shaped bit line contact, and the tapered shape capacitor structures, exposing top surface portions of polysilicon word line structures. The selective etch back procedure also results in formation of insulator spacers on the sides of the tapered bit line contact, and capacitor structures, allowing a subsequent salicide procedure to form metal suicide layers only on the exposed top surfaces of the DRAM word line, bit line contact, and capacitor structures.
摘要翻译：已经开发了一种用于将自对准硅化物层形成在DRAM字线结构上以及位线接触结构上的过程。该工艺具有嵌入锥形位线接触件的绝缘体层的选择性回蚀和锥形形状电容器结构，暴露多晶硅字线结构的顶表面部分。选择性回蚀程序还导致在锥形位线接触和电容器结构的侧面上形成绝缘体间隔物，并且允许随后的自对准硅化物程序仅在DRAM字线，位线的暴露的顶表面上形成金属硅化物层接触和电容器结构。

5. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

6. 发明授权

US06569732B1 Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell 有权
标题翻译：在SRAM单元中制造埋层堆叠电容器结构期间，能够消除多晶硅残渣和硅损伤的集成工艺顺序
公开(公告)号：US06569732B1
公开(公告)日：2003-05-27
申请号：US10262926
申请日：2002-10-02
申请人： Min-Hsiung Chiang , Chung-Wei Chang , Kuo-Chyuan Tzeng
发明人： Min-Hsiung Chiang , Chung-Wei Chang , Kuo-Chyuan Tzeng
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L27/11
摘要： A process sequence for fabricating a buried stack capacitor structure, to be used as a component in a memory cell such as a one transistor SRAM cell, has been developed. The process features formation of a self-aligned opening used to accommodate a subsequent buried stack capacitor structure, with the self-aligned opening defined via selective dry and wet etch procedures, employed to avoid damage to regions of a semiconductor substrate which become exposed at the conclusion of the definition procedure. In addition the process sequence allows a smooth, top surface topography to be present during definition of a polysilicon storage node structure in the self-aligned opening, allowing unwanted portions of polysilicon to be easily removed, reducing the risk of polysilicon stringers.
摘要翻译：已经开发了用于制造用作诸如一晶体管SRAM单元的存储单元中的组件的掩埋叠层电容器结构的工艺顺序。该工艺特征是形成自对准开口，用于容纳随后的掩埋堆叠电容器结构，其中采用经由选择性干法和湿式蚀刻工艺限定的自对准开口，以避免损坏在该位置处露出的半导体衬底的区域定义程序的结论。此外，工艺顺序允许在自对准开口中的多晶硅存储节点结构的定义期间存在平滑的顶表面形貌，从而允许容易去除多晶硅的不希望的部分，从而降低多晶硅桁架的风险。

7. 发明授权

US6025279A Method of reducing nitride and oxide peeling after planarization using an anneal 失效
标题翻译：使用退火在平坦化后还原氮化物和氧化物剥离的方法
公开(公告)号：US6025279A
公开(公告)日：2000-02-15
申请号：US86824
申请日：1998-05-29
申请人： Min-Hsiung Chiang , Chen-Jong Wang , Jenn Ming Huang
发明人： Min-Hsiung Chiang , Chen-Jong Wang , Jenn Ming Huang
IPC分类号： H01L21/3105 , H01L21/314 , H01L21/02
CPC分类号： H01L21/31053
摘要： A method of rapid thermal annealing (RTA) a TEOS oxide layer 50 that underlies a silicon nitride stop layer 60. The RTA of the TEOS-Oxide ILD layer 50 prevents the nitride stop layer 60 and oxide ILD layer 50 from peeling in subsequent thermal steps. The process comprises providing a semiconductor structure 10 with an uneven surface; forming an interlevel dielectric layer 50 composed of PE-TEOS oxide over the structure 10; rapid thermal annealing (RTA) the third interlevel dielectric layer 50 at a temperature between about 850 and 1015.degree. C. for a time between about 10 and 50 seconds; depositing a silicon nitride layer 60 over the third interlevel dielectric layer 50; and planarizing the silicon nitride layer 60 and the third interlevel dielectric layer 50.
摘要翻译：快速热退火（RTA）在氮化硅阻挡层60下面的TEOS氧化物层50的方法.TEOS-氧化物ILD层50的RTA防止氮化物阻挡层60和氧化物ILD层50在随后的热步骤中剥离。该方法包括提供具有不平坦表面的半导体结构10; 在结构10上形成由PE-TEOS氧化物构成的层间电介质层50; 快速热退火（RTA）第三层间介电层50在约850至1015℃的温度下约10至50秒之间的时间; 在第三层间介质层50上沉积氮化硅层60; 并且平坦化氮化硅层60和第三层间电介质层50。

8. 发明授权

US06600228B2 Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule 有权
标题翻译：顶部金属水平的锁孔预填充光致抗蚀剂，以防止钝化损坏，即使是严重的顶级金属规则
公开(公告)号：US06600228B2
公开(公告)日：2003-07-29
申请号：US09929676
申请日：2001-08-15
申请人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
发明人： Yu-Hua Lee , Min-Hsiung Chiang , Jenn Ming Huang
IPC分类号： H01L214763
CPC分类号： H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 Å to about 500 Å and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 Å to about 1200 Å below the narrow neck.
摘要翻译：光致抗蚀剂层的平坦化表面形成在形成在覆盖层中的孔的上方的层上，保形的氮化硅层，其又形成在半导体器件的表面上的SOG层之间的金属化中的锁孔上方。在覆盖氮化硅上方形成毯状的第一光致抗蚀剂层，以填充由孔引起的对表面的损伤。然后剥离第一光致抗蚀剂层，留下填充孔的第一光致抗蚀剂层的残留部分。接下来，在覆盖层上方形成毯状的第二光致抗蚀剂层。该孔具有宽度从大约至大约500埃的颈部，并且该孔具有深的袋状间隙，其横截面的宽度从窄到90度到大约在1200度。

9. 发明授权

US06020236A Method to form capacitance node contacts with improved isolation in a DRAM process 有权
标题翻译：在DRAM工艺中形成具有改进的隔离的电容节点触点的方法
公开(公告)号：US06020236A
公开(公告)日：2000-02-01
申请号：US257723
申请日：1999-02-25
申请人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James Wu , Wen-Chuan Chiang , Min-Hsiung Chiang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug. A lining layer of silicon nitride is deposited and etched to remain only on the vertical interior surfaces of the second contact hole. A second polysilicon layer is deposited to fill the second contact hole. The second polysilicon layer and the second interpoly isolation layer are planarized. The fabrication of the integrated circuit device is completed.
摘要翻译：描述了在DRAM处理中形成具有改进的隔离的电容节点触点的方法。在半导体衬底上形成隔离层。形成第一接触孔并填充多晶硅插塞，并且隔离层和多晶硅插塞的顶表面被抛光到平坦表面。沉积第一间隔隔离层。沉积停止层。沉积覆盖层。沉积第一多晶硅层。第一多晶硅层被蚀刻以形成特征。沉积第二个互隔离层。第二间隔隔离层被平坦化。第二接触孔被蚀刻穿过第二多晶硅隔离层和封盖层。暴露的第一多晶硅材料被回蚀刻到第二接触孔的垂直侧。停止层和第一互隔离层被蚀刻到多晶硅插塞的顶表面。沉积和蚀刻氮化硅的内衬层以仅保留在第二接触孔的垂直内表面上。沉积第二多晶硅层以填充第二接触孔。第二多晶硅层和第二多晶硅隔离层被平坦化。完成集成电路器件的制造。

10. 发明申请

US20050112876A1 Method to form a robust TiCI4 based CVD TiN film 审中-公开
标题翻译：形成坚固的TiCI4基CVD TiN膜的方法
公开(公告)号：US20050112876A1
公开(公告)日：2005-05-26
申请号：US10723237
申请日：2003-11-26
申请人： Chih-Ta Wu , Kuo Yin Lin , Min-Hsiung Chiang
发明人： Chih-Ta Wu , Kuo Yin Lin , Min-Hsiung Chiang
IPC分类号： C23C16/34 , C23C16/56 , H01L21/20 , H01L21/768
CPC分类号： C23C16/56 , C23C16/34 , H01L21/76843 , H01L21/76856 , H01L21/76862
摘要： A method is described for a plasma treatment of a TiCl4 based CVD deposited TiN layer that reduces stress, lowers resistivity, and improves film stability. Resistivity is stable in an air ambient for up to 48 hours after the plasma treatment. A TiN layer is treated with a N-containing plasma that includes N2, NH3, or N2H4 at a temperature between 500° C. and 700° C. Optionally, H2 may be added to N2 in the plasma step which removes chloride impurities and densifies the TiN layer. The TiN layer may serve as a barrier layer, an ARC layer, or as a bottom electrode in a MIM capacitor. An improved resistance of the treated TiN layer to oxidation during formation of an oxide based insulator layer and a lower leakage current in the MIM capacitor is also achieved.
摘要翻译：描述了一种用于等离子体处理基于TiCl 4的CVD沉积TiN层的方法，其降低应力，降低电阻率并提高膜的稳定性。等离子体处理后电阻率在空气环境中稳定长达48小时。用含N的等离子体处理TiN层，该等离子体包括N 2，NH 3或N 2 H 4，在500℃至700℃之间的温度下，可以在等离子体步骤中将H 2 N加入到N 2 N中，除去氯化物杂质并致密化 TiN层。 TiN层可以用作MIM电容器中的阻挡层，ARC层或底电极。还实现了在形成氧化物基绝缘体层期间处理的TiN层对氧化的改善的电阻和MIM电容器中较低的漏电流。

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