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1. 发明申请

US20060180944A1 Flip chip ball grid array package with constraint plate 审中-公开
公开(公告)号：US20060180944A1
公开(公告)日：2006-08-17
申请号：US11400316
申请日：2006-04-10
申请人： Kuo-Chin Chang , Simon Lu
发明人： Kuo-Chin Chang , Simon Lu
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/49833 , H01L23/562 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2224/0401
摘要： A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface of the substrate. A constraint member is secured to the lower surface of the substrate so that the constraint member has a degree of rigidity to reduce warpage due to thermal expansion mismatches between at least the microelectronic element and the substrate.

2. 发明申请

US20060043602A1 Flip chip ball grid array package with constraint plate 审中-公开
标题翻译：倒装芯片球栅阵列封装带约束板
公开(公告)号：US20060043602A1
公开(公告)日：2006-03-02
申请号：US10932005
申请日：2004-09-02
申请人： Kuo-Chin Chang , Simon Lu
发明人： Kuo-Chin Chang , Simon Lu
IPC分类号： H01L23/48
CPC分类号： H01L23/49838 , H01L23/49816 , H01L23/49833 , H01L23/562 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2224/0401
摘要： A flip chip ball grid array package is provided. In one embodiment, a flip chip ball grid array package comprises a substrate having an upper surface and a lower surface opposite the upper surface and a microelectronic element comprising a set of solder balls being secured to the upper surface of the substrate. A constraint member is secured to the lower surface of the substrate so that the constraint member has a degree of rigidity to reduce warpage due to thermal expansion mismatches between at least the microelectronic element and the substrate.
摘要翻译：提供倒装芯片球栅阵列封装。在一个实施例中，倒装芯片球栅阵列封装包括具有上表面和与上表面相对的下表面的衬底，以及包括一组焊球固定到衬底的上表面的微电子元件。约束构件被固定到基板的下表面，使得约束构件具有刚度以减少由于至少微电子元件和基板之间的热膨胀错配引起的翘曲。

3. 发明授权

US08976529B2 Lid design for reliability enhancement in flip chip package 有权
标题翻译：封装设计，用于倒装芯片封装的可靠性提升
公开(公告)号：US08976529B2
公开(公告)日：2015-03-10
申请号：US13007249
申请日：2011-01-14
申请人： Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
发明人： Wen-Yi Lin , Po-Yao Lin , Tsung-Shu Lin , Kuo-Chin Chang , Shou-Yi Wang
IPC分类号： H05K7/20 , H01L23/16 , H01L23/055 , H01L23/00
CPC分类号： H01L23/16 , H01L23/055 , H01L23/562 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
摘要： In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.
摘要翻译：在包装结构中，加强环在第一包装部件的顶表面上结合并结合。第二包装部件在第一包装部件的顶部表面上结合并且被加强环环绕。金属盖已经结合到加强环上。金属盖具有通孔。

4. 发明申请

US20110057313A1 Enhanced Copper Posts for Wafer Level Chip Scale Packaging 有权
标题翻译：晶圆级芯片尺寸封装的增强铜柱
公开(公告)号：US20110057313A1
公开(公告)日：2011-03-10
申请号：US12899168
申请日：2010-10-06
申请人： Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
发明人： Kuo-Chin Chang , Han-Ping Pu , Pei-Haw Tsao
IPC分类号： H01L23/498
CPC分类号： H01L24/11 , H01L24/81 , H01L2224/0231 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/1148 , H01L2224/116 , H01L2224/11902 , H01L2224/13019 , H01L2224/13076 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/81801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00
摘要： An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.
摘要翻译：描述了增强的晶片级芯片级封装（WLCSP）铜电极柱，其具有从电极柱的顶部突出的一个或多个引脚。当焊球焊接到柱上时，引脚被封装在焊料材料内。引脚不仅在焊球和电极柱之间的焊接接头上增加剪切强度，而且由于电极柱/销组合和焊球之间的表面积增加，也产生更可靠的电连接。此外，产生不规则形状的焊点阻碍了可能在焊接接头形成的金属间化合物（IMC）层中形成的裂纹的传播。

5. 发明授权

US07662665B2 Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging 有权
标题翻译：用于制造包括用于倒装芯片封装的应力消除层的半导体封装的方法
公开(公告)号：US07662665B2
公开(公告)日：2010-02-16
申请号：US11655844
申请日：2007-01-22
申请人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
发明人： Chen-Shien Chen , Kuo-Chin Chang , Szu-Wei Lu , Pei-Haw Tsao , Chung-Yu Wang , Han-Liang Tseng , Mirng-Ji Lii
IPC分类号： H01L21/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L23/49827 , H01L24/02 , H01L24/11 , H01L24/16 , H01L2224/02319 , H01L2224/02321 , H01L2224/0401 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.
摘要翻译：提供一种制造半导体封装的方法。在一个实施例中，提供其上具有多个暴露的导电层的半导体芯片。提供具有第一表面和第二表面的第一基底，所述第一表面在其下具有多个暴露的通孔塞。半导体芯片被接合到第一基板，其中多个暴露的导体层被对准并且与暴露的通孔塞的表面接触。然后去除第一基板的第二表面的一部分以暴露多个通孔塞的相对端。在多个通孔塞的相对端的表面上形成多个UBM层。多个焊料凸起形成并安装在UBM层上。提供具有第一表面和第二表面的第二基底，焊料凸块安装到第二基底的第一表面。多个焊球形成并安装在第二基板的第二表面上。第三衬底安装到焊球。

6. 发明申请

US20080023850A1 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US20080023850A1
公开(公告)日：2008-01-31
申请号：US11493375
申请日：2006-07-26
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装衬底优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。硅基薄封装衬底可以用作半导体芯片的载体。

7. 发明申请

US20070069366A1 Novel constraint stiffener design 有权
标题翻译：新型约束加强筋设计
公开(公告)号：US20070069366A1
公开(公告)日：2007-03-29
申请号：US11237924
申请日：2005-09-29
申请人： Kuo-Chin Chang , Ching-Yu Ni
发明人： Kuo-Chin Chang , Ching-Yu Ni
IPC分类号： H01L23/12
CPC分类号： H01L23/16 , H01L23/36 , H01L23/562 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/15311
摘要： A constraint stiffener for reinforcing an integrated circuit package is provided. In one embodiment, the constraint stiffener comprises a rigid, planar base element for bonding to an integrated circuit substrate. The base element has a plurality of elongated support members, and the base element has an opening therein for surrounding an integrated circuit. The base element and support members reduce warpage due to thermal expansion mismatches between at least the integrated circuit and the substrate. In one embodiment, the elongated support members are detachable from the corners of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the corners of the base element. In yet another embodiment, the elongated support members are detachable from about the midsections of the base element. In another embodiment, the elongated support members have means for attaching and detaching to the midsections of the base element.
摘要翻译：提供了用于加强集成电路封装的约束加强件。在一个实施例中，约束加强件包括用于结合到集成电路基板的刚性平面基座元件。基座元件具有多个细长的支撑构件，并且基座元件具有用于围绕集成电路的开口。基部元件和支撑构件由于至少集成电路和基板之间的热膨胀失配而减少翘曲。在一个实施例中，细长支撑构件可从基座元件的角部拆卸。在另一个实施例中，细长支撑构件具有用于附接和分离到基部元件的角部的装置。在另一个实施例中，细长的支撑构件可从基部元件的中央部分的周围拆卸。在另一个实施例中，细长的支撑构件具有用于附接和分离到基部元件的中部的装置。

8. 发明申请

US20060055032A1 Packaging with metal studs formed on solder pads 审中-公开
标题翻译：包装在焊盘上形成金属螺柱
公开(公告)号：US20060055032A1
公开(公告)日：2006-03-16
申请号：US10941586
申请日：2004-09-14
申请人： Kuo-Chin Chang , Kuo-Ning Chiang
发明人： Kuo-Chin Chang , Kuo-Ning Chiang
IPC分类号： H01L23/48
CPC分类号： H05K3/3436 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/13099 , H01L2224/13147 , H01L2224/136 , H01L2224/16225 , H01L2224/73253 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/351 , H05K1/111 , H05K2201/0367 , Y02P70/611 , Y02P70/613 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05099
摘要： A semiconductor assembly has solder bumps with increased reliability. One embodiment of an assembly comprises a first substrate having at least one conductive pad on its surface; a second substrate having at least one conductive pad on its surface; at least one conductive stud; and at least one solder bump in contact with the conductive pad on the first substrate, and in contact with the conductive pad of the second substrate, and formed around the at least one conductive stud. Methods for providing these assemblies are included.
摘要翻译：半导体组件具有增加的可靠性的焊料凸块。组件的一个实施例包括在其表面上具有至少一个导电垫的第一衬底; 第二基板，其表面上具有至少一个导电垫; 至少一个导电螺柱; 以及与所述第一基板上的所述导电焊盘接触并与所述第二基板的所述导电焊盘接触并且形成在所述至少一个导电螺柱周围的至少一个焊料凸块。包括提供这些组件的方法。

9. 发明授权

US08704383B2 Silicon-based thin substrate and packaging schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US08704383B2
公开(公告)日：2014-04-22
申请号：US13452562
申请日：2012-04-20
申请人： Szu-Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu-Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

10. 发明申请

US20120199974A1 Silicon-Based Thin Substrate and Packaging Schemes 有权
标题翻译：硅基薄基板和封装方案
公开(公告)号：US20120199974A1
公开(公告)日：2012-08-09
申请号：US13452562
申请日：2012-04-20
申请人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
发明人： Szu Wei Lu , Clinton Chao , Ann Luh , Tjandra Winata Karta , Jerry Tzou , Kuo-Chin Chang
IPC分类号： H01L23/48
CPC分类号： H01L23/147 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L25/0655 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01327 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/157 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
摘要翻译：硅基薄封装衬底用于封装半导体芯片。硅基薄封装基板优选具有小于约200μm的厚度。在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。半导体芯片可以安装在焊料凸块上。硅基薄封装衬底可以用作半导体芯片的载体。

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