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    • 4. 发明授权
    • Method and apparatus for driving an electric motor
    • 用于驱动电动机的方法和装置
    • US5847521A
    • 1998-12-08
    • US684343
    • 1996-07-19
    • Masatoshi MorikawaKunio SekiYasuhiko Kokami
    • Masatoshi MorikawaKunio SekiYasuhiko Kokami
    • H02P6/06H02P6/00H02P6/08H02P7/00
    • H02P6/085H02P6/34
    • A motor drive method and apparatus for reducing noise of a motor. The motor drive apparatus includes first, second and third half bridge circuits. Each of the first, second and third half bridge circuits includes a first transistor which is adapted to form a current path between a first operational potential and an output terminal thereof and a second transistor which is adapted to form a current path between a second operational potential and the output terminal thereof. Each of the output terminals are connected to the corresponding drive coil of a motor. Each of the first and second transistors includes a control terminal to which a control signal is supplied. The motor drive apparatus detects a counter-induced voltage of the drive coil corresponding to the second half bridge circuit by supplying control signals to the first and second transistors thereof for making each current path therein a non-conducting state, and for forming current paths in the first transistor of the first half bridge circuit and in the second transistor of the third half bridge circuit respectively. Further the motor drive apparatus cuts off the current path of the first transistor in the first half bridge circuit, forms it and cuts it off again by supplying a control signal thereto after start of supplying a control signal for forming the current path of the first transistor in the second half bridge circuit. A control signal for forming the current path is supplied to the control terminal of the second transistor in the third half bridge circuit.
    • 一种用于降低电动机噪声的电动机驱动方法和装置。 电机驱动装置包括第一,第二和第三半桥电路。 第一,第二和第三半桥电路中的每一个包括第一晶体管,其适于在第一操作电位和其输出端之间形成电流路径,以及第二晶体管,其适于在第二操作电位之间形成电流路径 及其输出端。 每个输出端子连接到电动机的相应的驱动线圈。 第一和第二晶体管中的每一个包括控制端子,控制端子被提供给控制端子。 马达驱动装置通过向其第一和第二晶体管提供控制信号来检测与第二半桥电路相对应的驱动线圈的反感应电压,以使其中的每个电流路径处于非导通状态,并且用于形成电流路径 第一半桥电路的第一晶体管和第三半桥电路的第二晶体管。 此外,马达驱动装置切断第一半桥电路中的第一晶体管的电流路径,并且在开始提供用于形成第一晶体管的电流路径的控制信号之后,通过向其提供控制信号来形成它并再次切断 在后半桥电路中。 用于形成电流路径的控制信号被提供给第三半桥电路中的第二晶体管的控制端。
    • 6. 发明授权
    • Transistor power amplifier circuit
    • 晶体管功率放大电路
    • US4503478A
    • 1985-03-05
    • US52207
    • 1979-06-26
    • Kunio SekiRitsuji Takeshita
    • Kunio SekiRitsuji Takeshita
    • H03F1/42H03F1/52H03F3/20H03F3/30H02H7/20
    • H03F1/52
    • Two output transistors constituting a push-pull output amplifier circuit are connected in series between a power supply and a grounded point, and an output terminal is disposed at a point where the two output transistors are commonly connected. An operation detector circuit detects the operation of one output transistor. A level detector circuit detects a d-c voltage level at the output terminal. The two output transistors are driven by a drive circuit in a push-pull manner. The output of the operation detector circuit and the output of the level detector circuit control the drive circuit via a control circuit. When the operation detector circuit detected the fact that the operation of one output transistor has deviated beyond a predetermined detection level, the control circuit works to confine the operation of the abovementioned output transistor within a predetermined restriction level via the drive circuit. The power loss in the restriction level is smaller than the power loss in the detection level. During a period in which the output terminal is short-circuited to the grounded point in a d-c manner, the level detector circuit so controls the control circuit that the operation of the abovementioned one output transistor is confined within the restriction level.
    • 构成推挽输出放大器电路的两个输出晶体管串联在电源和接地点之间,并且输出端子设置在两个输出晶体管共同连接的点处。 操作检测器电路检测一个输出晶体管的操作。 电平检测器电路检测输出端子处的d-c电压电平。 两个输出晶体管以推挽方式由驱动电路驱动。 操作检测器电路的输出和电平检测器电路的输出通过控制电路来控制驱动电路。 当操作检测器电路检测到一个输出晶体管的操作已经偏离超过预定检测电平的事实时,控制电路通过驱动电路将上述输出晶体管的操作限制在预定限制电平内。 限制级别的功率损耗小于检测级别的功率损耗。 在输出端子以d-c方式与接地点短路的期间中,电平检测电路对控制电路进行控制,使得上述一个输出晶体管的动作被限制在限制电平内。
    • 7. 发明授权
    • Protecting circuit
    • 保护电路
    • US4258406A
    • 1981-03-24
    • US52208
    • 1979-06-26
    • Kunio Seki
    • Kunio Seki
    • G05F1/573H03F1/42H03F1/52H02H7/20
    • G05F1/573H03F1/52
    • A first resistor and a second resistor are connected in series across the collector and emitter of a transistor that is to be protected thereby to detect a voltage across the collector and emitter thereof, as well as to detect a collector current or an emitter current thereof, and a third resistor is connected to be collector or the emitter of the transistor that is to be protected. A detector transistor is driven by a voltage produced across the second and third transistors. A fourth resistor is connected between the collector and the base of the detector transistor, one end of the fourth resistor connected to the base of the detector transistor being connected to a constant-current circuit, and the other end of the fourth resistor connected to the collector of the detector transistor being connected to the base of a control transistor. The emitter of the control transistor is connected to the collector or the emitter of the transistor that is to be protected via the third resistor. The collector of the control transistor directly or indirectly controls the base current of the transistor that is to be protected.
    • 第一电阻器和第二电阻器串联连接在待保护的晶体管的集电极和发射极上,以便检测其集电极和发射极两端的电压,以及检测集电极电流或发射极电流, 并且第三电阻器被连接成要被保护的晶体管的集电极或发射极。 检测器晶体管由跨越第二和第三晶体管产生的电压驱动。 第四电阻器连接在检测器晶体管的集电极和基极之间,连接到检测器晶体管的基极的第四电阻器的一端连接到恒流电路,而第四电阻器的另一端连接到 检测器晶体管的集电极连接到控制晶体管的基极。 控制晶体管的发射极通过第三电阻连接到待保护的晶体管的集电极或发射极。 控制晶体管的集电极直接或间接地控制要被保护的晶体管的基极电流。
    • 8. 发明授权
    • Transistor circuit including source voltage ripple removal
    • 晶体管电路包括源电压纹波去除
    • US4017749A
    • 1977-04-12
    • US669699
    • 1976-03-23
    • Kunio SekiYukio SuzukiYoshio Sakamoto
    • Kunio SekiYukio SuzukiYoshio Sakamoto
    • H02J1/02H03F1/30H03F3/30H03K17/00
    • H03F3/3091H03F1/302
    • In a transistor circuit comprising a monolithic semiconductor integrated circuit including at least one first conductivity type transistor having a base connected to a signal input terminal, a collector connected to an output terminal and also connected to a source voltage supply terminal through a collector load resistance, and an emitter connected to a reference potential through an emitter resistance, and a voltage dividing resistance circuit connected externally to the integrated circuit to establish a base-emitter biasing voltage of the first conductivity type transistor, another resistance element is provided between the source voltage supply terminal and the load resistance and a second conductivity type transistor is provided with the emitter and the collector connected to the interconnection point of the two resistances and the reference potential, respectively, and the base connected to the emitter of the first conductivity type transistor, integrating a source voltage ripple removing circuit in the integrated circuit. This transistor circuit is adapted for a high output power integrated circuit and provides a wide range of operable source voltage as well as the removal of the ac ripple voltage component of the voltage source and the reduction in the number of external connecting pins.
    • 在包括单片半导体集成电路的晶体管电路中,该单片半导体集成电路包括至少一个第一导电型晶体管,其具有连接到信号输入端子的基极,集电极连接到输出端子,并且还通过集电极负载电阻连接到源极电压源端子, 以及通过发射极电阻连接到参考电位的发射极和连接到集成电路外部的分压电阻电路,以建立第一导电类型晶体管的基极 - 发射极偏置电压,另一个电阻元件设置在源极电压源 端子和负载电阻,第二导电类型晶体管分别设置有与两个电阻和基准电位的互连点连接的发射极和集电极,并且连接到第一导电型晶体管的发射极的基极集成 源电压纹波 去除集成电路中的电路。 该晶体管电路适用于高输出功率集成电路,并提供宽范围的可操作的源电压以及去除电压源的交流纹波电压分量和减少外部连接引脚的数量。
    • 10. 发明授权
    • Acoustic monolithic power semiconductor integrated circuit and acoustic
system using the same
    • 声学单片功率半导体集成电路和声学系统使用相同
    • US4321428A
    • 1982-03-23
    • US87765
    • 1979-10-24
    • Kunio Seki
    • Kunio Seki
    • H03F3/30H03F3/68H04S5/02H03F3/00
    • H03F3/3088H03F3/68H04S5/02
    • An acoustic monolithic IC, which is enabled by a simple modification of the external circuit thereof to realize either the amplification of the left and right channels of stereophonic signals or the application to a balanced transformer-less (BTL) amplifier circuit, is composed of first and second differential amplifier circuits each having non-inverting and inverting inputs and of first and second amplifier output circuits each having non-inverting and inverting inputs.The first differential amplifier circuit has its non-inverting and inverting inputs led as the first and second input terminals of the acoustic monolithic IC to the outside thereof whereas the second differential amplifier circuit has its non-inverting and inverting inputs led as the third and fourth input terminals of the acoustic monolithic IC to the outside thereof.The output signals of the first and second differential amplifier circuits are impressed upon the non-inverting inputs of the first and second amplifier output circuits, respectively. The inverting inputs of the first and second amplifier output circuits are led as first and second feedback terminals to the outside of the acoustic monolithic IC so as to determine the gains and output DC levels of those amplifier output circuits.The output terminals of the first and second amplifier output circuits are led as the first and second output terminals of the acoustic monolithic IC to the outside thereof.
    • 通过其外部电路的简单修改实现立体声信号的左声道和右声道的放大或者应用于平衡无变压器(BTL)放大器电路的声学单片IC由第一 每个具有非反相和反相输入的第二差分放大器电路以及第一和第二放大器输出电路各自具有非反相和反相输入。 第一差分放大器电路具有作为声单体IC的第一和第二输入端到其外部的非反相和反相输入端,而第二差分放大器电路的反相和反相输入被引导为第三和第四 声学单片IC的输入端到其外部。 第一和第二差分放大器电路的输出信号分别施加在第一和第二放大器输出电路的同相输入端上。 第一和第二放大器输出电路的反相输入端作为第一和第二反馈端子被引导到声学单片IC的外部,以便确定那些放大器输出电路的增益和输出DC电平。 第一和第二放大器输出电路的输出端作为声音单体IC的第一和第二输出端被引导到其外部。