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    • 7. 发明申请
    • DRIVER CIRCUIT WITH PULL DOWN NPN TRANSISTOR
    • 带有下拉NPN晶体管的驱动电路
    • WO98051006A1
    • 1998-11-12
    • PCT/US1998/008850
    • 1998-05-01
    • H03F1/32H03F3/30
    • H03F1/32H03F3/3088
    • A driver circuit with pull down npn transistor drives an output voltage signal in response to an input voltage signal, without high-speed pnp transistors. A first npn transistor (22) provides current to the output node when the output node is at a level equal to and less than the level of the input voltage signal less a base-to-emitter junction drop across the first npn transistor (22). A second npn transistor (20) sinks current from the output node when the output node is at a level greater than the level of the input voltage signal less the base-to-emitter junction drop across the first npn transistor (22). The second npn transistor (20) is controlled by a level of a control node (38). When the level of the output node is greater than the level of the input voltage signal less the base-to-emitter junction drop, the first npn transistor (22) is turned off and the level of the control node (38) is charged up by a current source (26). When the level of the control node (38) reaches a sufficient level, the second npn transistor (20) is turned on and the level of the output voltage signal is decreased.
    • 具有下拉npn晶体管的驱动器电路驱动输出电压信号,以响应输入电压信号,而不需要高速pnp晶体管。 当输出节点处于等于和小于输入电压信号的电平的电平时,第一npn晶体管(22)向输出节点提供电流,减去跨越第一npn晶体管(22)的基极 - 发射极结降, 。 当输出节点处于大于输入电压信号的电平的电平时,第二npn晶体管(20)从输出节点吸收电流,减去跨越第一npn晶体管(22)的基极 - 发射极结降。 第二npn晶体管(20)由控制节点(38)的电平控制。 当输出节点的电平大于输入电压信号的电平时,基极 - 发射极结降低,第一npn晶体管(22)截止,并且控制节点(38)的电平被充电 通过电流源(26)。 当控制节点(38)的电平达到足够的电平时,第二npn晶体管(20)导通,输出电压信号的电平降低。
    • 9. 发明公开
    • Improvements in or relating to an operational amplifier
    • 在Bezug auf einenOperationverstärker中进行操作
    • EP1014567A2
    • 2000-06-28
    • EP99204415.6
    • 1999-12-20
    • Texas Instruments Incorporated
    • Corsi, MarcoEscobar-Bowser, Priscilla
    • H03F3/30
    • H03F1/3217H03F3/3088
    • Responsive to an external load, an output stage (201) of an amplifier (200) in accordance with the present invention provides a current boosting scheme capable of generating a large output current while maintaining a low quiescent current. The output stage (201) includes a sink control circuit (204) coupled to the input terminal (202) for receiving the output of the input amplifier stage. A translinear loop circuit (210) is coupled to the sink control circuit (204), for receiving the sink pass-through current and for producing a source pass-through current. A current mirror circuit (222) is coupled to the translinear loop circuit (210) for receiving the source pass-through and for producing a bias current output therefrom. An output driver (230) is coupled to the current mirror circuit (222) and the sink control circuit (204), wherein the output driver (230) receives the bias output current and the sink pass-though current to provide an output current. Accordingly, the output stage (200) provides a power efficient bias solution for driving low impedance loads with enhanced sourcing capability of high positive power supply rejection ratio, high output voltage swing, and stable negative feedback architecture.
    • 响应于外部负载,根据本发明的放大器(200)的输出级(201)提供能够在保持低静态电流的同时产生大的输出电流的电流升压方案。 输出级(201)包括耦合到输入端(202)的接收器控制电路(204),用于接收输入放大级的输出。 交流线路环路电路(210)耦合到宿控制电路(204),用于接收宿直通电流并产生源直通电流。 电流镜电路(222)耦合到用于接收源极穿过并用于产生从其输出的偏置电流的跨导线圈电路(210)。 输出驱动器(230)耦合到电流镜电路(222)和吸收器控制电路(204),其中输出驱动器(230)接收偏置输出电流和吸收通过电流以提供输出电流。 因此,输出级(200)提供了用于驱动具有高正电源抑制比,高输出电压摆幅和稳定的负反馈架构的增强的采购能力的低阻抗负载的功率有效的偏置解决方案。