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1. 发明授权

US07705422B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

2. 发明申请

US20060237819A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060237819A1
公开(公告)日：2006-10-26
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

3. 发明授权

US07202567B2 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07202567B2
公开(公告)日：2007-04-10
申请号：US11090112
申请日：2005-03-28
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L29/00 , H01L29/861
CPC分类号： H01L27/016 , H01L23/5223 , H01L28/55 , H01L2924/0002 , Y10S257/923 , Y10S257/924 , H01L2924/00
摘要： A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased. Accordingly, the MIM capacitive element with a large capacitance can be manufactured with a high yield.
摘要翻译：在半导体衬底上提供较低的互连。 MIM电容元件设置在第一层间绝缘膜上，其中下互连被埋入，并且包括下电极，上电极和夹在其间的电介质膜。在MIM电容元件被埋置的第二层间绝缘膜上设置上互连。触点电连接下电极和上互连。下电极主要由Al形成，使得它们的电阻低于阻挡金属，并且应力值也较低。因此，可以扩大用于电连接触点的下电极的面积，同时抑制它们对电荷累积的影响和下电极与绝缘膜之间的紧密接触。此外，由于电阻降低，所以能够提高下部电极的厚度。因此，可以以高产率制造具有大电容的MIM电容元件。

4. 发明授权

US07154158B2 Semiconductor device having MIM structure resistor 有权
标题翻译：具有MIM结构电阻器的半导体器件
公开(公告)号：US07154158B2
公开(公告)日：2006-12-26
申请号：US10964623
申请日：2004-10-15
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L27/0688 , H01L27/0629 , H01L28/20 , H01L28/40
摘要： As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure comprises a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also comprises a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition. Therefore, even if the signal of higher frequency is applied to the metal resistor, the resistor structure lower electrode is hardly affected by the parasitic capacitance thereof due to its floating condition, thereby providing improved high frequency characteristics of the device including such metal resistor.
摘要翻译：对于半导体衬底上的电阻器，除了形成多晶硅电阻器之外，还需要获得可以在用于制造半导体的预备工艺的后半部分中形成的金属电阻器，该多晶硅电阻器形成在第一一半的初步过程。具有MIM结构的电容器包括下电极，电容绝缘膜和上电极，所有这些按顺序依次形成。具有MIM结构的电阻器结构还包括下电极，电容绝缘膜和电阻器，所有这些按顺序依次形成。在这种情况下，应当选择其偏置条件，使得MIM结构电阻器的电阻器结构下电极不耦合到任何电位，并且处于浮置状态。因此，即使将较高频率的信号施加到金属电阻器，由于电阻结构下电极由于其浮动状态而几乎不受其寄生电容的影响，从而提供包括这种金属电阻器的器件的改进的高频特性。

5. 发明申请

US20050139956A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050139956A1
公开(公告)日：2005-06-30
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L21/8234 , H01L21/20 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

6. 发明授权

US08378454B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

7. 发明授权

US07432170B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

8. 发明申请

US20050218520A1 Semiconductor device and manufacturing method for the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050218520A1
公开(公告)日：2005-10-06
申请号：US11090112
申请日：2005-03-28
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L27/01 , H01L27/108
CPC分类号： H01L27/016 , H01L23/5223 , H01L28/55 , H01L2924/0002 , Y10S257/923 , Y10S257/924 , H01L2924/00
摘要： A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased. Accordingly, the MIM capacitive element with a large capacitance can be manufactured with a high yield.
摘要翻译：在半导体衬底上提供较低的互连。 MIM电容元件设置在第一层间绝缘膜上，其中下互连被埋入，并且包括下电极，上电极和夹在其间的电介质膜。在MIM电容元件被埋置的第二层间绝缘膜上设置上互连。触点电连接下电极和上互连。下电极主要由Al形成，使得它们的电阻低于阻挡金属，并且应力值也较低。因此，可以扩大用于电连接触点的下电极的面积，同时抑制它们对电荷累积的影响和下电极与绝缘膜之间的紧密接触。此外，由于电阻降低，所以能够提高下部电极的厚度。因此，可以以高产率制造具有大电容的MIM电容元件。

9. 发明申请

US20050082639A1 Semiconductor device having MIM structure resistor 有权
标题翻译：具有MIM结构电阻器的半导体器件
公开(公告)号：US20050082639A1
公开(公告)日：2005-04-21
申请号：US10964623
申请日：2004-10-15
申请人： Kuniko Kikuta , Makoto Nakayama
发明人： Kuniko Kikuta , Makoto Nakayama
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L21/20 , H01L29/00
CPC分类号： H01L27/0688 , H01L27/0629 , H01L28/20 , H01L28/40
摘要： As for the resistor on the semiconductor substrate, it is required to achieve obtaining a metal resistor, which can be formed in the latter half of a preliminary process for manufacturing a semiconductor, in addition to forming a polysilicon resistor, which is formed in the first half of the preliminary process. A capacitor having MIM structure includes a lower electrode, a capacitive insulating film and an upper electrode, all of which are sequentially formed in this sequence. A resistor structure having MIM structure also includes a lower electrode, a capacitive insulating film and a resistor, all of which are sequentially formed in this sequence. In this case, the biasing conditions thereof should be selected so that the resistor structure lower electrode of the MIM structure resistor is not coupled to any electric potential, and is in a floating condition.
摘要翻译：对于半导体衬底上的电阻器，除了形成多晶硅电阻器之外，还需要获得可以在用于制造半导体的预备工艺的后半部分中形成的金属电阻器，该多晶硅电阻器形成在第一一半的初步过程。具有MIM结构的电容器包括下电极，电容绝缘膜和上电极，所有这些按顺序依次形成。具有MIM结构的电阻器结构还包括下电极，电容绝缘膜和电阻器，所有这些按顺序依次形成。在这种情况下，应当选择其偏置条件，使得MIM结构电阻器的电阻器结构下电极不耦合到任何电位，并且处于浮置状态。

10. 发明授权

US07986026B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07986026B2
公开(公告)日：2011-07-26
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

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