专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06751123B2 Storage device counting error correction 有权
标题翻译：存储设备计数错误更正
公开(公告)号：US06751123B2
公开(公告)日：2004-06-15
申请号：US10430345
申请日：2003-05-07
申请人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
发明人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
IPC分类号： G11C1606
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F2201/88 , G11C29/42 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.
摘要翻译：一种半导体存储装置，其基于先前记录的纠错计数确定在从非易失性半导体存储器读出的数据的错误校正时的错误原因，并选择数据刷新处理或替代处理执行。当检测到错误时，更正的数据被重写，以防止由于意外原因而导致错误的再次发生。如果确定错误的再现频率高并且错误是由于存储介质的劣化，则基于纠错计数，执行替代处理。

2. 发明授权

US06339546B1 Storage device counting error correction 有权
公开(公告)号：US06339546B1
公开(公告)日：2002-01-15
申请号：US09662926
申请日：2000-09-15
申请人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
发明人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
IPC分类号： G11C1606
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F2201/88 , G11C29/42 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.

3. 发明授权

US06584015B2 Storage device counting error correction 有权
公开(公告)号：US06584015B2
公开(公告)日：2003-06-24
申请号：US10246694
申请日：2002-09-19
申请人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
发明人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
IPC分类号： G11C1604
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F2201/88 , G11C29/42 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.

4. 发明授权

US06480416B2 Storage device counting error correction 有权
标题翻译：存储设备计数错误更正
公开(公告)号：US06480416B2
公开(公告)日：2002-11-12
申请号：US10020223
申请日：2001-12-18
申请人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
发明人： Kunihiro Katayama , Takayuki Tamura , Yusuke Jono , Motoki Kanamori , Atsushi Shikata
IPC分类号： G11C1606
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F2201/88 , G11C29/42 , G11C29/76 , G11C2029/0411 , G11C2029/1208
摘要： A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.
摘要翻译：一种半导体存储装置，其基于先前记录的纠错计数确定在从非易失性半导体存储器读出的数据的错误校正时的错误原因，并选择数据刷新处理或替代处理执行。当检测到错误时，更正的数据被重写，以防止由于意外原因而导致错误的再次发生。如果确定错误的再现频率高并且错误是由于存储介质的劣化，则基于纠错计数，执行替代处理。

5. 发明授权

US07339833B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07339833B2
公开(公告)日：2008-03-04
申请号：US11481782
申请日：2006-07-07
申请人： Yusuke Jono , Takashi Kono , Tadaaki Yamauchi
发明人： Yusuke Jono , Takashi Kono , Tadaaki Yamauchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0458 , G11C16/0491 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.
摘要翻译：使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。电容元件的电容值根据写入数据的值而变化。实现了以高精度写入多值数据的非易失性半导体存储器件。

6. 发明申请

US20070008781A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070008781A1
公开(公告)日：2007-01-11
申请号：US11481782
申请日：2006-07-07
申请人： Yusuke Jono , Takashi Kono , Tadaaki Yamauchi
发明人： Yusuke Jono , Takashi Kono , Tadaaki Yamauchi
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0458 , G11C16/0491 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： Using charges accumulated in a capacitance element connected to a drain side node of a memory cell, data is written in accordance with source side injection method. The capacitance value of the capacitance element is changed in accordance with the value of write data. A non-volatile semiconductor memory device allowing writing of multi-valued data at high speed with high precision is achieved.
摘要翻译：使用与连接到存储单元的漏极侧节点的电容元件中累积的电荷，根据源侧注入方式写入数据。电容元件的电容值根据写入数据的值而变化。实现了以高精度写入多值数据的非易失性半导体存储器件。

7. 发明申请

US20060023515A1 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20060023515A1
公开(公告)日：2006-02-02
申请号：US11189977
申请日：2005-07-27
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C7/10
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
摘要翻译：非易失性存储器包括各自具有依次重复串联连接的第一控制晶体管，存储晶体管，第二控制晶体管和存储器晶体管的电路。在控制晶体管导通时，在与串行方向相交的方向上形成反转层。选择电路选择放置在第一控制晶体管下方的反相层及其对应的读/写电路的连接。放置在与存储晶体管相邻的两侧的控制晶体管被导通以执行读取。放置在从一侧到另一侧观察的第二控制晶体管的两侧上的第一控制晶体管被导通，以通过右和左存储晶体管中的一个来执行向左和右存储晶体管中的另一个的写入。选择电路以这样的方式连接读/写电路和反转层，即在相同存储晶体管的读和写中使用相同的读/写电路。

8. 发明申请

US20080316806A1 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US20080316806A1
公开(公告)日：2008-12-25
申请号：US12213195
申请日：2008-06-16
申请人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
发明人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0023 , G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.
摘要翻译：相变存储器件包括：相变元件，用于通过改变电阻状态来重写地存储数据; 存储单元，布置在字线和位线的交点处，并由所述相变元件和串联连接的二极管形成; 形成在存储单元下方的扩散层中的选择晶体管，用于响应于连接到栅极的字线的电位选择性地控制二极管的阳极与地线之间的电连接; 以及预充电电路，用于将对应于未选择字线的存储单元下面的扩散层预充电到预定电压，并且用于将与所选择的字线相对应的存储单元下面的扩散层与预定电压断开。

9. 发明申请

US20080094905A1 Nonvolatile Memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20080094905A1
公开(公告)日：2008-04-24
申请号：US11952693
申请日：2007-12-07
申请人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
发明人： Koji Kishi , Hideaki Kurata , Satoshi Noda , Yusuke Jono
IPC分类号： G11C16/06
CPC分类号： G11C16/0491 , G11C16/0425 , G11C16/0458 , G11C16/10 , G11C16/26
摘要： A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
摘要翻译：非易失性存储器包括各自具有依次重复串联连接的第一控制晶体管，存储晶体管，第二控制晶体管和存储器晶体管的电路。在控制晶体管导通时，在与串行方向相交的方向上形成反转层。选择电路选择放置在第一控制晶体管下方的反相层及其对应的读/写电路的连接。放置在与存储晶体管相邻的两侧的控制晶体管被导通以执行读取。放置在从一侧到另一侧观察的第二控制晶体管的两侧上的第一控制晶体管被导通，以通过右和左存储晶体管中的一个来执行向左和右存储晶体管中的另一个的写入。选择电路以这样的方式连接读/写电路和反转层，即在相同存储晶体管的读和写中使用相同的读/写电路。

10. 发明授权

US08054679B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08054679B2
公开(公告)日：2011-11-08
申请号：US12213195
申请日：2008-06-16
申请人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
发明人： Kiyoshi Nakai , Shuichi Tsukada , Yusuke Jono
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C11/5678 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.
摘要翻译：相变存储器件包括：相变元件，用于通过改变电阻状态来重写地存储数据; 存储单元，布置在字线和位线的交点处，并由所述相变元件和串联连接的二极管形成; 形成在存储单元下方的扩散层中的选择晶体管，用于响应于连接到栅极的字线的电位选择性地控制二极管的阳极与地线之间的电连接; 以及预充电电路，用于将对应于未选择字线的存储单元下面的扩散层预充电到预定电压，并且用于将与所选择的字线相对应的存储单元下面的扩散层与预定电压断开。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式