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    • 4. 发明授权
    • Method for fixation onto layer comprising amorphous carbon film, and laminate
    • 固定在包含无定形碳膜的层和层压板上的方法
    • US09132609B2
    • 2015-09-15
    • US13582731
    • 2011-03-03
    • Kunihiko ShibusawaTakeshi Sato
    • Kunihiko ShibusawaTakeshi Sato
    • B32B9/00B32B9/04C01B31/02C23C16/26B32B37/16
    • C23C16/26B32B9/04B32B37/16C01B32/05Y10T156/10Y10T428/30
    • A method for fixation, onto a layer comprising an amorphous carbon film and provided on a base material, of a layer comprising a material condensation-reacting with hydroxyl groups on a surface of the amorphous carbon film, whereby, in the layer comprising an amorphous carbon film and provided on the base material, the amorphous carbon film can have a holding power which is strong enough to fix the layer comprising a material condensation-reacting with a hydroxyl group on the surface of the amorphous carbon film and can have uniformity of the holding power. Si and O are added into the layer comprising an amorphous carbon film to thereby improve adhesion durability and binding uniformity of the layer comprising a material condensation-reacting with a hydroxyl group. Particularly, by using a fluorine-based silane coupling agent, it is possible to impart high functions such as water repellency/oil repellency, abrasion resistance, chemical resistance, low friction properties and non-tackiness to the amorphous carbon film.
    • 一种在包含无定形碳膜并在基材上提供的层上固定包含在非晶碳膜的表面上与羟基缩合反应的材料的层的方法,由此在包含无定形碳的层中 膜,并且设置在基材上,非晶碳膜可以具有足够强的保持力,以将包含与羟基缩合反应的材料的层固定在非晶碳膜的表面上,并且可以具有均匀的保持 功率。 将Si和O添加到包含无定形碳膜的层中,从而提高包含与羟基缩合反应的材料的层的粘合耐久性和粘合均匀性。 特别是通过使用氟系硅烷偶联剂,能够赋予无定形碳膜更高的功能性,例如防水性/拒油性,耐磨性,耐化学性,低摩擦性和非粘性。
    • 7. 发明授权
    • Non-volatile semiconductor memory using split bit lines
    • 使用分割位线的非易失性半导体存储器
    • US06188605B1
    • 2001-02-13
    • US09257242
    • 1999-02-25
    • Hidemi NomuraAkira YoneyamaKunihiko Shibusawa
    • Hidemi NomuraAkira YoneyamaKunihiko Shibusawa
    • G11C1604
    • G11C16/0425G11C7/18H01L27/115
    • A first bit line BLa0 and a second bit line BLb0 are arranged for a single bit line BL0. A memory cell array is divided into a plurality of memory cell array blocks. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. On the further outsides arranged are an electrode wiring 20 for applying a predetermined potential ARGBD and electrode wirings 21 and 22 for applying the control signals DCBLa and DCBLb. A plurality of units, each including the memory cell array block, the control transistors and control signals, are arranged. Main bit lines each passing through these units are extended so that they are connected to the select transistors of each unit pattern. In such a configuration, the capacitive load of bit lines owing to high integration of a non-volatile semiconductor memory is reduced, thereby realizing the high speed operation of the memory. In addition, an increase of the chip size can be prevented and easiness of a pattern layout can be assured.
    • 对于单个位线BL0布置第一位线BLa0和第二位线BLb0。 存储单元阵列被分成多个存储单元阵列块。 在存储单元阵列11的两个相对侧,选择晶体管Q0,Q1和Q4,Q5,并且布置放电晶体管Q2,Q3和Q6,Q7。 在另外的外部布置有用于施加预定电位ARGBD的电极布线20和用于施加控制信号DCBLa和DCBLb的电极布线21和22。 布置有包括存储单元阵列块,控制晶体管和控制信号的多个单元。 通过这些单元的主位线被延伸,使得它们连接到每个单元图案的选择晶体管。 在这样的结构中,由于非易失性半导体存储器的高集成度,位线的电容性负载降低,从而实现存储器的高速操作。 此外,可以防止芯片尺寸的增加,并且可以确保图案布局的容易性。
    • 8. 发明申请
    • SCREEN-PRINTING STENCIL HAVING AMORPHOUS CARBON FILMS AND MANUFACTURING METHOD THEREFOR
    • 具有非晶形碳膜的印刷液晶片及其制造方法
    • US20130220152A1
    • 2013-08-29
    • US13700061
    • 2011-04-01
    • Kunihiko Shibusawa
    • Kunihiko Shibusawa
    • B41F15/34
    • B41F15/34B41C1/148B41N1/248H05K3/1225
    • [Object] To provide a screen printing stencil including an amorphous carbon film, such as a DLC film, and a water-oil-repellent layer provided on at least part of the amorphous carbon film so as to exhibit high fixability.[Solution] A screen printing plate 10 of an embodiment of the present invention includes a mesh 16 fixed to a frame body 12; an emulsion layer 14 which fills up the mesh 16 and has a print pattern opening 18; an amorphous carbon film formed on at least part of the surface of an inner wall 22 of the print pattern opening 18 and composed of at least one element of silicon, oxygen, and nitrogen; and a thin film 20 of a fluorine-containing silane coupling agent formed on at least part of the amorphous carbon film.
    • 提供包含无定形碳膜(如DLC膜)和设置在至少部分无定形碳膜上的防水疏水层的丝网印刷模版,从而具有高定影性。 [解决方案]本发明的实施例的丝网印版10包括固定到框体12上的网16; 乳剂层14,其填充网状物16并具有印刷图案开口18; 形成在印刷图案开口18的内壁22的表面的至少一部分上并由硅,氧和氮的至少一种元素构成的无定形碳膜; 以及形成在非晶碳膜的至少一部分上的含氟硅烷偶联剂的薄膜20。
    • 9. 发明授权
    • Non-volatile semiconductor memory
    • 非易失性半导体存储器
    • US6157569A
    • 2000-12-05
    • US251406
    • 1999-02-17
    • Hidemi NomuraKunihiko ShibusawaAkira Yoneyama
    • Hidemi NomuraKunihiko ShibusawaAkira Yoneyama
    • G11C5/02G11C7/18G11C8/12G11C16/04H01L27/115
    • G11C8/12G11C16/0425G11C5/02G11C7/18H01L27/115
    • A memory cell array 11 is divided into plural blocks in such a manner that a first and a second split bit line BLa and BLb0 are provided for a single main bit BL0. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. Further, on both sides of the memory cell array, a wiring 20 at a predetermined potential ARGND and wirings 21 and 22 for select control signals DCBLa and DCBLb are arranged. A second gate electrode wiring 23 connects the gate of the first select transistor Q0, that of the second discharge transistor (corresponding to Q3) relative to the adjacent main bit line and the wiring 21. A first gate electrode wiring 25 connects the gate of the second select transistor Q1, that of the first discharge transistor Q2 and the wiring 21. In such a configuration, the capacity of a non-volatile semiconductor memory is increased so that the capacitive load of bit lines can be reduced and the operation speed can be enhanced. The increase in the chip size can be prevented and easiness of the layout of the pattern of the memory can be assured.
    • 存储单元阵列11被分成多个块,以便为单个主位BL0提供第一和第二分割位线BLa和BLb0。 在存储单元阵列11的两个相对侧,选择晶体管Q0,Q1和Q4,Q5,并且布置放电晶体管Q2,Q3和Q6,Q7。 此外,在存储单元阵列的两侧布置有预定电位ARGND的布线20和用于选择控制信号DCBLa和DCBLb的布线21和22。 第二栅极布线23将第一选择晶体管Q0的栅极,第二放电晶体管的栅极(对应于Q3)相对于相邻的主位线和布线21连接。第一栅极布线25将栅极 第二选择晶体管Q1,第一放电晶体管Q2和布线21的晶体管Q1。在这种配置中,非易失性半导体存储器的容量增加,从而可以降低位线的电容性负载,并且可以将操作速度 增强。 可以防止芯片尺寸的增加,并且可以确保存储器的图案的布局的容易性。