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1. 发明授权

US06317362B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06317362B1
公开(公告)日：2001-11-13
申请号：US09614778
申请日：2000-07-12
申请人： Hidemi Nomura , Akira Yoneyama
发明人： Hidemi Nomura , Akira Yoneyama
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： A pair of reference cells 77 and 78 has the same structure as that of memory cells 51 and 52 and is arranged in the same direction on a semiconductor substrate. The memory cell 51 and the reference cell 77 (even cell) are coincident in their source/drain direction. The memory cell 52 and the reference cell 78 (odd cell) are coincident in their source/drain direction. A selection circuit 79 selects the reference cell 77 when the memory cell 51 is selected, whereas the selection circuit 79 selects the reference cell 78 when the memory cell 52 is selected. In this configuration, a semiconductor memory device is provided which can prevent erroneous read and provide stable read-out characteristic irrespectively of a change in a manufacturing process.
摘要翻译：一对参考单元77和78具有与存储单元51和52相同的结构，并且在半导体衬底上沿相同的方向布置。存储单元51和参考单元77（均匀单元）在其源极/漏极方向上重合。存储单元52和参考单元78（奇数单元）在它们的源极/漏极方向上重合。当选择存储单元51时，选择电路79选择参考单元77，而选择电路79在选择存储单元52时选择参考单元78。在这种结构中，提供了一种半导体存储器件，其可以防止错误读取并且提供稳定的读出特性，而与制造过程的变化无关。

2. 发明授权

US6157569A Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US6157569A
公开(公告)日：2000-12-05
申请号：US251406
申请日：1999-02-17
申请人： Hidemi Nomura , Kunihiko Shibusawa , Akira Yoneyama
发明人： Hidemi Nomura , Kunihiko Shibusawa , Akira Yoneyama
IPC分类号： G11C5/02 , G11C7/18 , G11C8/12 , G11C16/04 , H01L27/115
CPC分类号： G11C8/12 , G11C16/0425 , G11C5/02 , G11C7/18 , H01L27/115
摘要： A memory cell array 11 is divided into plural blocks in such a manner that a first and a second split bit line BLa and BLb0 are provided for a single main bit BL0. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. Further, on both sides of the memory cell array, a wiring 20 at a predetermined potential ARGND and wirings 21 and 22 for select control signals DCBLa and DCBLb are arranged. A second gate electrode wiring 23 connects the gate of the first select transistor Q0, that of the second discharge transistor (corresponding to Q3) relative to the adjacent main bit line and the wiring 21. A first gate electrode wiring 25 connects the gate of the second select transistor Q1, that of the first discharge transistor Q2 and the wiring 21. In such a configuration, the capacity of a non-volatile semiconductor memory is increased so that the capacitive load of bit lines can be reduced and the operation speed can be enhanced. The increase in the chip size can be prevented and easiness of the layout of the pattern of the memory can be assured.
摘要翻译：存储单元阵列11被分成多个块，以便为单个主位BL0提供第一和第二分割位线BLa和BLb0。在存储单元阵列11的两个相对侧，选择晶体管Q0，Q1和Q4，Q5，并且布置放电晶体管Q2，Q3和Q6，Q7。此外，在存储单元阵列的两侧布置有预定电位ARGND的布线20和用于选择控制信号DCBLa和DCBLb的布线21和22。第二栅极布线23将第一选择晶体管Q0的栅极，第二放电晶体管的栅极（对应于Q3）相对于相邻的主位线和布线21连接。第一栅极布线25将栅极第二选择晶体管Q1，第一放电晶体管Q2和布线21的晶体管Q1。在这种配置中，非易失性半导体存储器的容量增加，从而可以降低位线的电容性负载，并且可以将操作速度增强。可以防止芯片尺寸的增加，并且可以确保存储器的图案的布局的容易性。

3. 发明授权

US06188605B1 Non-volatile semiconductor memory using split bit lines 失效
标题翻译：使用分割位线的非易失性半导体存储器
公开(公告)号：US06188605B1
公开(公告)日：2001-02-13
申请号：US09257242
申请日：1999-02-25
申请人： Hidemi Nomura , Akira Yoneyama , Kunihiko Shibusawa
发明人： Hidemi Nomura , Akira Yoneyama , Kunihiko Shibusawa
IPC分类号： G11C1604
CPC分类号： G11C16/0425 , G11C7/18 , H01L27/115
摘要： A first bit line BLa0 and a second bit line BLb0 are arranged for a single bit line BL0. A memory cell array is divided into a plurality of memory cell array blocks. On both opposite sides of the memory cell array 11, select transistors Q0, Q1 and Q4, Q5 and discharge transistors Q2, Q3 and Q6, Q7 are arranged. On the further outsides arranged are an electrode wiring 20 for applying a predetermined potential ARGBD and electrode wirings 21 and 22 for applying the control signals DCBLa and DCBLb. A plurality of units, each including the memory cell array block, the control transistors and control signals, are arranged. Main bit lines each passing through these units are extended so that they are connected to the select transistors of each unit pattern. In such a configuration, the capacitive load of bit lines owing to high integration of a non-volatile semiconductor memory is reduced, thereby realizing the high speed operation of the memory. In addition, an increase of the chip size can be prevented and easiness of a pattern layout can be assured.
摘要翻译：对于单个位线BL0布置第一位线BLa0和第二位线BLb0。存储单元阵列被分成多个存储单元阵列块。在存储单元阵列11的两个相对侧，选择晶体管Q0，Q1和Q4，Q5，并且布置放电晶体管Q2，Q3和Q6，Q7。在另外的外部布置有用于施加预定电位ARGBD的电极布线20和用于施加控制信号DCBLa和DCBLb的电极布线21和22。布置有包括存储单元阵列块，控制晶体管和控制信号的多个单元。通过这些单元的主位线被延伸，使得它们连接到每个单元图案的选择晶体管。在这样的结构中，由于非易失性半导体存储器的高集成度，位线的电容性负载降低，从而实现存储器的高速操作。此外，可以防止芯片尺寸的增加，并且可以确保图案布局的容易性。

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