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1. 发明申请

US20130113053A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US20130113053A1
公开(公告)日：2013-05-09
申请号：US13288041
申请日：2011-11-03
申请人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
发明人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/265 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.
摘要翻译：半导体结构包括基板，电介质层和氟化金属层。电介质层位于衬底上。氟化金属层位于电介质层上。此外，本发明还提供了形成所述半导体结构的半导体工艺。

2. 发明授权

US09006092B2 Semiconductor structure having fluoride metal layer and process thereof 有权
标题翻译：具有氟化物金属层的半导体结构及其工艺
公开(公告)号：US09006092B2
公开(公告)日：2015-04-14
申请号：US13288041
申请日：2011-11-03
申请人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
发明人： Kun-Hsien Lin , Chun-Hsien Lin , Hsin-Fu Huang
IPC分类号： H01L21/02 , H01L21/3205 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/66 , H01L21/265 , H01L29/51
CPC分类号： H01L21/823842 , H01L21/265 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.
摘要翻译：半导体结构包括基板，电介质层和氟化物金属层。电介质层位于衬底上。氟化金属层位于电介质层上。此外，本发明还提供了形成所述半导体结构的半导体工艺。

3. 发明申请

US20120326243A1 TRANSISTOR HAVING ALUMINUM METAL GATE AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：具有铝金属栅的晶体管及其制造方法
公开(公告)号：US20120326243A1
公开(公告)日：2012-12-27
申请号：US13165795
申请日：2011-06-22
申请人： Hsin-Fu Huang , Chi-Mao Hsu , Min-Chuan Tsai , Chin-Fu Lin , Chun-Hsien Lin
发明人： Hsin-Fu Huang , Chi-Mao Hsu , Min-Chuan Tsai , Chin-Fu Lin , Chun-Hsien Lin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on the substrate. The aluminum metal gate includes a work function tuning layer and an aluminum metal layer disposed orderly on the high-k gate dielectric layer, where the aluminum metal layer comprises a first aluminum metal layer and a second aluminum metal layer. Furthermore, the source/drain region is disposed in the substrate at each of two sides of the aluminum metal gate.
摘要翻译：具有铝金属栅极的晶体管包括衬底，高k栅极电介质层，铝金属栅极和源极/漏极区域。高k栅极电介质层设置在基板上。铝金属栅包括工作功能调谐层和铝金属层，该金属层有序地设置在高k栅介质层上，铝金属层包括第一铝金属层和第二铝金属层。此外，源极/漏极区域设置在铝金属栅极的两侧中的每一侧的基板中。

4. 发明申请

US20130228921A1 SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：基板结构及其制造方法
公开(公告)号：US20130228921A1
公开(公告)日：2013-09-05
申请号：US13534620
申请日：2012-06-27
申请人： Liang-Yi Hung , Yu-Cheng Pai , Wei-Chung Hsiao , Chun-Hsien Lin , Ming-Chen Sun
发明人： Liang-Yi Hung , Yu-Cheng Pai , Wei-Chung Hsiao , Chun-Hsien Lin , Ming-Chen Sun
IPC分类号： H01L23/485 , H01L21/768 , H01L21/60 , H01L23/488
CPC分类号： H01L23/49811 , H01L23/3128 , H01L23/49816 , H01L24/32 , H01L24/48 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H05K3/244 , H05K3/3436 , H05K3/3478 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure.
摘要翻译：基板结构包括基板主体和形成在基板主体上的多个导电焊盘，每个具有顺序层叠的第一铜层，镍层，第二铜层和金层。第二铜层的厚度小于第一铜层的厚度。因此，本发明有效地增强了将要安装在导电焊盘上的导电焊盘和焊球之间的接合强度，并且延长了衬底结构的持续时间。

5. 发明授权

US08452439B2 Device performance parmeter tuning method and system 有权
标题翻译：设备性能参数调节方法和系统
公开(公告)号：US08452439B2
公开(公告)日：2013-05-28
申请号：US13048282
申请日：2011-03-15
申请人： Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
发明人： Sunny Wu , Chun-Hsien Lin , Kun-Ming Chen , Dung-Yian Hsieh , Hui-Ru Lin , Jo Fei Wang , Jong-I Mou , I-Ching Chu
IPC分类号： G06F19/00 , G01N37/00 , G06F11/30 , G21C17/00
CPC分类号： H01L22/20 , G01R31/2894 , H01L22/14
摘要： A method comprises computing respective regression models for each of a plurality of failure bins based on a plurality of failures identified during wafer electrical tests. Each regression model outputs a wafer yield measure as a function of a plurality of device performance variables. For each failure bin, sensitivity of the wafer yield measure to each of the plurality of device performance variables is determined, and the device performance variables are ranked with respect to sensitivity of the wafer yield measure. A subset of the device performance variables which have highest rankings and which have less than a threshold correlation with each other are selected. The wafer yield measures for each failure bin corresponding to one of the selected subset of device performance variables are combined, to provide a combined wafer yield measure. At least one new process parameter value is selected to effect a change in the one device performance variable, based on the combined wafer yield measure. The at least one new process parameter value is to be used to process at least one additional wafer.
摘要翻译：一种方法包括基于在晶片电测试期间识别的多个故障来计算多个故障仓中的每一个的相应回归模型。每个回归模型输出作为多个设备性能变量的函数的晶片产量测量。对于每个故障仓，确定晶片产量测量对多个器件性能变量中的每一个的灵敏度，并且相对于晶片产量测量的灵敏度对器件性能变量进行排序。选择具有最高排名并且彼此具有小于阈值相关性的设备性能变量的子集。组合对应于所选择的设备性能变量子集之一的每个故障仓的晶片产量测量，以提供组合晶片产量测量。选择至少一个新的过程参数值，以基于组合的晶片产量测量来实现一个器件性能变量的变化。至少一个新的过程参数值将用于处理至少一个附加晶片。

6. 发明授权

US08426277B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08426277B2
公开(公告)日：2013-04-23
申请号：US13241232
申请日：2011-09-23
申请人： Chien-Liang Lin , Shih-Hung Tsai , Chun-Hsien Lin , Te-Lin Sun , Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang
发明人： Chien-Liang Lin , Shih-Hung Tsai , Chun-Hsien Lin , Te-Lin Sun , Shao-Wei Wang , Ying-Wei Yen , Yu-Ren Wang
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/3247 , H01L29/66795 , H01L29/7854
摘要： A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.
摘要翻译：半导体工艺包括以下步骤。提供基板。至少在基板上形成翅片状结构，在基板上形成氧化层，而不形成翅片状结构。进行热处理工艺以在鳍状结构的侧壁的至少一部分上形成熔融层。

7. 发明申请

US20120313178A1 SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有金属门的半导体器件及其制造方法
公开(公告)号：US20120313178A1
公开(公告)日：2012-12-13
申请号：US13158479
申请日：2011-06-13
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC分类号： H01L21/3205 , H01L29/78
CPC分类号： H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
摘要翻译：一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层，在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层栅极沟槽，以及去除牺牲掩模层。第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。第一导电类型和第二导电类型是互补的。

8. 发明授权

US08295965B2 Semiconductor processing dispatch control 有权
标题翻译：半导体处理调度控制
公开(公告)号：US08295965B2
公开(公告)日：2012-10-23
申请号：US12839014
申请日：2010-07-19
申请人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
发明人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G05B19/4187 , G05B19/042 , G05B19/41865 , G05B2219/2602 , G05B2219/32237 , G05B2219/32423 , G05B2219/45031 , G05B2219/50065 , Y02P90/20
摘要： An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
摘要翻译：实施例是用于半导体处理控制的方法。该方法包括基于处理的晶片的参数从多个处理阶段识别关键处理阶段，基于该参数来预测由密钥处理阶段处理的晶片的趋势以及多个处理阶段中的一些，以及调度晶片转换为调谐处理阶段中的第一多个工具之一。根据趋势确定第一组多个工具中的一个。

9. 发明授权

US08292309B2 Supporting device with wheels 有权
标题翻译：带轮的支撑装置
公开(公告)号：US08292309B2
公开(公告)日：2012-10-23
申请号：US12701688
申请日：2010-02-08
申请人： Chen-Lu Fan , Chih-Kun Shih , Chun-Hsien Lin
发明人： Chen-Lu Fan , Chih-Kun Shih , Chun-Hsien Lin
IPC分类号： B62D33/02
CPC分类号： B60B37/10
摘要： A supporting device includes a tray, a plurality of wheel assemblies, a handle, and a handgrip. The tray is configured for supporting a payload. The wheel assemblies are secured to the tray, and each wheel assembly includes a wheel. Each wheel is capable of rotating about a first axis. The wheel assemblies are rotatable between a first position and a second position, and a distance between each wheel and the tray in the first position is smaller than a distance between each wheel and the tray in the second position. The handle is attached to the tray and configured to urge the wheel assemblies to rotate from the first position to the second position. The handgrip is attached to the tray and configured to urge the wheel assemblies to rotate from the second position to the first position.
摘要翻译：支撑装置包括托盘，多个轮组件，手柄和手柄。托盘配置为支持有效载荷。车轮组件被固定到托盘，并且每个车轮组件包括车轮。每个车轮能够围绕第一轴线旋转。车轮组件可在第一位置和第二位置之间转动，并且在第一位置的每个车轮和托盘之间的距离小于在第二位置的每个车轮和托盘之间的距离。手柄连接到托盘并构造成推动车轮组件从第一位置旋转到第二位置。手柄附接到托盘并且构造成推动车轮组件从第二位置旋转到第一位置。

10. 发明申请

US20120034747A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120034747A1
公开(公告)日：2012-02-09
申请号：US13277384
申请日：2011-10-20
申请人： Chun-Hsien Lin
发明人： Chun-Hsien Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/28088 , H01L21/28114 , H01L21/823807 , H01L21/82385 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/7833
摘要： A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.
摘要翻译：对半导体装置的制造方法进行说明。在基板上形成多晶硅层。多晶硅层掺杂有N型掺杂剂。然后去除多晶硅层的一部分以形成多个虚拟图案。每个虚拟图案具有布置在顶部和底部之间的顶部，底部和颈部，其中颈部的宽度比顶部的宽度窄。在基板上形成电介质层以覆盖设置在相邻虚设图案之间的基板，并且暴露每个虚设图案的顶部。此后，去除虚拟图案以在电介质层中形成多个沟槽。在沟槽中分别形成多个栅极结构。

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