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1. 发明授权

US09542238B2 Systems and methods for direct memory access coherency among multiple processing cores 有权
标题翻译：在多个处理核心之间直接存储器访问一致性的系统和方法
公开(公告)号：US09542238B2
公开(公告)日：2017-01-10
申请号：US13900761
申请日：2013-05-23
申请人： Kun Xu , Tommi M. Jokinen , Zheng Xu
发明人： Kun Xu , Tommi M. Jokinen , Zheng Xu
IPC分类号： G06F9/46 , G06F9/52 , G06F9/48 , G06F9/50
CPC分类号： G06F9/526 , G06F9/46 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52
摘要： A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.
摘要翻译：一种多核系统，被配置为执行多个任务并具有能够由第一核心的任务调度器选择由第一核执行的第一任务的信号引擎和直接存储器访问（DMA）引擎。响应于信号量锁定请求，第一核心的任务调度器将第一任务切换到非活动状态，并选择下一任务以由第一核执行。在信号引擎获取第一信号量的信号锁之后，向DMA引擎提供数据传输请求。响应于数据传输请求，DMA引擎将与锁定的第一信号量相关联的数据传送到第一核心的工作空间的入口。

2. 发明申请

US20140351825A1 SYSTEMS AND METHODS FOR DIRECT MEMORY ACCESS COHERENCY AMONG MULTIPLE PROCESSING CORES 有权
标题翻译：直接存储器访问多个处理系统的系统和方法
公开(公告)号：US20140351825A1
公开(公告)日：2014-11-27
申请号：US13900761
申请日：2013-05-23
申请人： Kun Xu , Tommi M. Jokinen , Zheng Xu
发明人： Kun Xu , Tommi M. Jokinen , Zheng Xu
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/46 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52
摘要： A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.
摘要翻译：一种多核系统，被配置为执行多个任务并具有能够由第一核心的任务调度器选择由第一核执行的第一任务的信号引擎和直接存储器访问（DMA）引擎。响应于信号量锁定请求，第一核心的任务调度器将第一任务切换到非活动状态，并选择下一任务以由第一核执行。在信号引擎获取第一信号量的信号锁之后，向DMA引擎提供数据传输请求。响应于数据传输请求，DMA引擎将与锁定的第一信号量相关联的数据传送到第一核心的工作空间的入口。

3. 发明申请

US20140219276A1 SYSTEM AND METHOD FOR MAINTAINING PACKET ORDER IN AN ORDERED DATA STREAM 有权
标题翻译：用于维护订单数据流中的分组订单的系统和方法
公开(公告)号：US20140219276A1
公开(公告)日：2014-08-07
申请号：US13760109
申请日：2013-02-06
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： H04L12/56
CPC分类号： H04L47/62
摘要： A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.
摘要翻译：源处理器可以在分组通信之前将数据流的每个分组划分成多个分段，从而允许以更小的分组发送分组。源处理器可以对于给定数据流并发地处理两个或更多个分组的分段，并且在每个分段报头中提供适当的上下文信息，以有助于顺序发送和接收由各个分段表示的分组。类似地，目的地处理器可以从源处理器接收用于有序数据流的分组分段分组，并且可以基于每个分段报头中的上下文信息来分配不同的上下文。当针对特定分组接收到最后一个分段时，特定分组的上下文被关闭，并且分组的描述符被发送到队列。传送数据包的最后一个段的顺序维护数据包之间的顺序。

4. 发明申请

US20130282933A1 DIRECT MEMORY ACCESS BUFFER UTILIZATION 有权
标题翻译：直接存储器访问缓冲器的使用
公开(公告)号：US20130282933A1
公开(公告)日：2013-10-24
申请号：US13454505
申请日：2012-04-24
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.
摘要翻译： DMA控制器根据数据段已经存储在缓冲区的时间长度，将缓冲区的空间分配给不同的DMA引擎。该分配确保与经历较高拥塞的目的地相关联的DMA引擎将被分配比经历较低拥塞的目的地更少的缓冲区空间。此外，DMA控制器能够适应转移目的地处的变化的拥塞状况。

5. 发明申请

US20120331187A1 BANDWIDTH CONTROL FOR A DIRECT MEMORY ACCESS UNIT WITHIN A DATA PROCESSING SYSTEM 有权
标题翻译：用于数据处理系统中的直接存储器访问单元的带宽控制
公开(公告)号：US20120331187A1
公开(公告)日：2012-12-27
申请号：US13168331
申请日：2011-06-24
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method for controlling bandwidth in a direct memory access (DMA) unit of a computer processing system, the method comprising: assigning a DMA job to a selected DMA engine; starting a source timer; and issuing a request to read a next section of data for the DMA job. If a sufficient amount of the data was not obtained, allowing the DMA engine to wait until the source timer reaches a specified value before continuing to read additional data for the DMA job.
摘要翻译：一种用于控制计算机处理系统的直接存储器访问（DMA）单元中的带宽的方法，所述方法包括：将DMA作业分配给所选择的DMA引擎; 启动源计时器; 并发出读取DMA作业的下一个数据部分的请求。如果未获得足够数量的数据，则允许DMA引擎等待，直到源定时器达到指定值，然后再继续读取DMA作业的其他数据。

6. 发明授权

US09195621B2 System and method for assigning memory access transfers between communication channels 有权
标题翻译：在通信通道之间分配存储器访问传输的系统和方法
公开(公告)号：US09195621B2
公开(公告)日：2015-11-24
申请号：US13838133
申请日：2013-03-15
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F13/16 , G06F13/28
CPC分类号： G06F13/1631 , G06F13/1647 , G06F13/28 , G06F2213/16 , G06F2213/2806
摘要： A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.
摘要翻译：通信信道控制器包括队列，存储器映射和调度器。存储在通信信道控制器处接收的第一存储器传送请求的队列。存储器映射存储用于标识与存储器相关联的存储器地址范围的信息。调度器将队列中的第一存储器传输的源地址与存储器映射中的存储器地址范围进行比较，以确定第一存储器传送请求的源地址是否针对存储器，并且响应于将第一存储器传送请求分配给多个通信信道的第一通信信道响应于第一通信信道具有其所有未完成的存储器事务到公共源地址组和作为源地址组的源地址页和第一存储器转移请求的源地址页。

7. 发明申请

US20150277972A1 SYSTEM AND METHOD FOR CONDITIONAL TASK SWITCHING DURING ORDERING SCOPE TRANSITIONS 有权
标题翻译：系统和方法在订单范围转换期间进行条件性的任务切换
公开(公告)号：US20150277972A1
公开(公告)日：2015-10-01
申请号：US14231784
申请日：2014-04-01
申请人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
发明人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
IPC分类号： G06F9/48
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/48
摘要： A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.
摘要翻译：数据处理系统包括处理器核心和订购范围管理器电路。处理器核心向当前订购范围发送当前由处理器核心执行的任务的第一订购范围标识符和用于任务的下一个订购范围的第二订购范围标识符的指示。订购范围管理器从处理器核心接收第一和第二订购范围标识符的指示，并且响应于确定第一任务是第一个转换顺序任务，向处理器核心提供无任务切换指示符第一个订购范围标识符，该处理器核心被授权执行下一个订购范围。处理器核心从当前订购范围内的执行转变为按顺序排序范围执行，而不响应于提供无任务切换指示器而执行任务切换。

8. 发明授权

US09128925B2 System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines 有权
标题翻译：通过设置具有与不同DMA引擎相关联的多个仲裁权重的DMA控制器来直接存储器访问缓冲器利用的系统和方法
公开(公告)号：US09128925B2
公开(公告)日：2015-09-08
申请号：US13454505
申请日：2012-04-24
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： G06F13/14 , G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.
摘要翻译： DMA控制器根据数据段已经存储在缓冲区的时间长度，将缓冲区的空间分配给不同的DMA引擎。该分配确保与经历较高拥塞的目的地相关联的DMA引擎将被分配比经历较低拥塞的目的地更少的缓冲区空间。此外，DMA控制器能够适应转移目的地处的变化的拥塞状况。

9. 发明授权

US09054998B2 System and method for maintaining packet order in an ordered data stream 有权
标题翻译：用于在有序数据流中维护分组顺序的系统和方法
公开(公告)号：US09054998B2
公开(公告)日：2015-06-09
申请号：US13760109
申请日：2013-02-06
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： H04L12/861 , H04L12/863
CPC分类号： H04L47/62
摘要： A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.
摘要翻译：源处理器可以在分组通信之前将数据流的每个分组划分成多个分段，从而允许以更小的分组发送分组。源处理器可以对于给定数据流并发地处理两个或更多个分组的分段，并且在每个分段报头中提供适当的上下文信息，以有助于顺序发送和接收由各个分段表示的分组。类似地，目的地处理器可以从源处理器接收用于有序数据流的分组分段分组，并且可以基于每个分段报头中的上下文信息来分配不同的上下文。当针对特定分组接收到最后一个分段时，特定分组的上下文被关闭，并且分组的描述符被发送到队列。传送数据包的最后一个段的顺序维护数据包之间的顺序。

10. 发明申请

US20140281043A1 SYSTEM AND METHOD FOR TRANSFERRING DATA BETWEEN COMPONENTS OF A DATA PROCESSOR 有权
标题翻译：用于传输数据处理器的组件之间的数据的系统和方法
公开(公告)号：US20140281043A1
公开(公告)日：2014-09-18
申请号：US13841916
申请日：2013-03-15
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.
摘要翻译：数据处理设备包括多个设备，处理器核心，存储器和队列管理器。处理器核心将一个或多个命令存储在由多个设备执行的存储器的命令队列中以实现数据传输路径。队列管理器存储多个设备中的每一个的帧队列。每个帧队列包括具有指向命令队列的地址的指针的第一字段和用于标识下一个序列帧队列的第二字段。第一设备将数据描述符存储在第二设备的帧队列中，以启动从第一设备到第二设备的数据传输。数据描述符包括用于指示从命令队列的地址到由第二设备执行的命令的位置的偏移值的字段。

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