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1. 发明申请

US20140219276A1 SYSTEM AND METHOD FOR MAINTAINING PACKET ORDER IN AN ORDERED DATA STREAM 有权
标题翻译：用于维护订单数据流中的分组订单的系统和方法
公开(公告)号：US20140219276A1
公开(公告)日：2014-08-07
申请号：US13760109
申请日：2013-02-06
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： H04L12/56
CPC分类号： H04L47/62
摘要： A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.
摘要翻译：源处理器可以在分组通信之前将数据流的每个分组划分成多个分段，从而允许以更小的分组发送分组。源处理器可以对于给定数据流并发地处理两个或更多个分组的分段，并且在每个分段报头中提供适当的上下文信息，以有助于顺序发送和接收由各个分段表示的分组。类似地，目的地处理器可以从源处理器接收用于有序数据流的分组分段分组，并且可以基于每个分段报头中的上下文信息来分配不同的上下文。当针对特定分组接收到最后一个分段时，特定分组的上下文被关闭，并且分组的描述符被发送到队列。传送数据包的最后一个段的顺序维护数据包之间的顺序。

2. 发明申请

US20130282933A1 DIRECT MEMORY ACCESS BUFFER UTILIZATION 有权
标题翻译：直接存储器访问缓冲器的使用
公开(公告)号：US20130282933A1
公开(公告)日：2013-10-24
申请号：US13454505
申请日：2012-04-24
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.
摘要翻译： DMA控制器根据数据段已经存储在缓冲区的时间长度，将缓冲区的空间分配给不同的DMA引擎。该分配确保与经历较高拥塞的目的地相关联的DMA引擎将被分配比经历较低拥塞的目的地更少的缓冲区空间。此外，DMA控制器能够适应转移目的地处的变化的拥塞状况。

3. 发明授权

US09733981B2 System and method for conditional task switching during ordering scope transitions 有权
公开(公告)号：US09733981B2
公开(公告)日：2017-08-15
申请号：US14300762
申请日：2014-06-10
申请人： Tommi M. Jokinen , Michael Kardonik , David B. Kramer , Peter W. Newton , John F. Pillar , Kun Xu
发明人： Tommi M. Jokinen , Michael Kardonik , David B. Kramer , Peter W. Newton , John F. Pillar , Kun Xu
IPC分类号： G06F9/48 , G06F9/46
CPC分类号： G06F9/4881 , G06F2209/484
摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

4. 发明申请

US20150355938A1 SYSTEM AND METHOD FOR CONDITIONAL TASK SWITCHING DURING ORDERING SCOPE TRANSITIONS 有权
标题翻译：系统和方法在订单范围转换期间进行条件性任务切换
公开(公告)号：US20150355938A1
公开(公告)日：2015-12-10
申请号：US14300762
申请日：2014-06-10
申请人： Tommi M. Jokinen , Michael Kardonik , David B. Kramer , Peter W. Newton , John F. Pillar , Kun Xu
发明人： Tommi M. Jokinen , Michael Kardonik , David B. Kramer , Peter W. Newton , John F. Pillar , Kun Xu
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F2209/484
摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.
摘要翻译：数据处理系统包括处理器核心和硬件模块。处理器内核在数据包上执行任务。订购范围管理器将第一个值存储在第一个存储位置。第一个值表示启用第一个排序范围中的第一个任务的独占执行。响应于接收到的放弃指示符，订购范围管理器将第二值存储在第一存储位置中。第二个值表示第一个排序范围中的第一个任务的排他性执行被禁用。

5. 发明授权

US08959278B2 System and method for scalable movement and replication of data 有权
标题翻译：可扩展运动和数据复制的系统和方法
公开(公告)号：US08959278B2
公开(公告)日：2015-02-17
申请号：US13106703
申请日：2011-05-12
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/02 , G06F12/0284 , G06F2212/254
摘要： A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.
摘要翻译：一种组播数据传输的方法，包括：访问源地址到存储源数据的映射存储器的源位置，将多个目的地地址存取到映射存储器的相应目的地位置，以及对源数据的至少一个部分中的每一个进行读取该部分使用源地址，将该部分存储到数据传输设备的本地存储器中，以及使用目的地地址将该部分从本地存储器写入映射的存储器中的每个目的地位置。可以提供单独的源和目的地属性，使得源和每个目的地可以具有用于读取和存储数据的不同属性。源和每个目的地可以具有可由支持数据传输的数据结构中提供的相应链路访问的任何数量的数据缓冲器。源数据可以分为部分和逐段处理。

6. 发明申请

US20140281335A1 SYSTEM AND METHOD FOR ASSIGNING MEMORY ACCESS TRANSFERS BETWEEN COMMUNICATION CHANNELS 有权
标题翻译：用于在通信通道之间分配存储器访问传输的系统和方法
公开(公告)号：US20140281335A1
公开(公告)日：2014-09-18
申请号：US13838133
申请日：2013-03-15
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F3/06
CPC分类号： G06F13/1631 , G06F13/1647 , G06F13/28 , G06F2213/16 , G06F2213/2806
摘要： A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.
摘要翻译：通信信道控制器包括队列，存储器映射和调度器。存储在通信信道控制器处接收的第一存储器传送请求的队列。存储器映射存储用于标识与存储器相关联的存储器地址范围的信息。调度器将队列中的第一存储器传输的源地址与存储器映射中的存储器地址范围进行比较，以确定第一存储器传送请求的源地址是否针对存储器，并且响应于将第一存储器传送请求分配给多个通信信道的第一通信信道响应于第一通信信道具有其所有未完成的存储器事务到公共源地址组和作为源地址组的源地址页和第一存储器转移请求的源地址页。

7. 发明申请

US20120290808A1 SYSTEM AND METHOD FOR SCALABLE MOVEMENT AND REPLICATION OF DATA 有权
标题翻译：用于可扩展运动和数据复制的系统和方法
公开(公告)号：US20120290808A1
公开(公告)日：2012-11-15
申请号：US13106703
申请日：2011-05-12
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F12/0284 , G06F2212/254
摘要： A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.
摘要翻译：一种组播数据传输的方法，包括：访问源地址到存储源数据的映射存储器的源位置，将多个目的地地址存取到映射存储器的相应目的地位置，以及对源数据的至少一个部分中的每一个进行读取该部分使用源地址，将该部分存储到数据传输设备的本地存储器中，以及使用目的地地址将该部分从本地存储器写入映射的存储器中的每个目的地位置。可以提供单独的源和目的地属性，使得源和每个目的地可以具有用于读取和存储数据的不同属性。源和每个目的地可以具有可由支持数据传输的数据结构中提供的相应链路访问的任何数量的数据缓冲器。源数据可以分为部分和逐段处理。

8. 发明授权

US09195621B2 System and method for assigning memory access transfers between communication channels 有权
标题翻译：在通信通道之间分配存储器访问传输的系统和方法
公开(公告)号：US09195621B2
公开(公告)日：2015-11-24
申请号：US13838133
申请日：2013-03-15
申请人： Kun Xu , Tommi M. Jokinen , David B. Kramer
发明人： Kun Xu , Tommi M. Jokinen , David B. Kramer
IPC分类号： G06F13/16 , G06F13/28
CPC分类号： G06F13/1631 , G06F13/1647 , G06F13/28 , G06F2213/16 , G06F2213/2806
摘要： A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.
摘要翻译：通信信道控制器包括队列，存储器映射和调度器。存储在通信信道控制器处接收的第一存储器传送请求的队列。存储器映射存储用于标识与存储器相关联的存储器地址范围的信息。调度器将队列中的第一存储器传输的源地址与存储器映射中的存储器地址范围进行比较，以确定第一存储器传送请求的源地址是否针对存储器，并且响应于将第一存储器传送请求分配给多个通信信道的第一通信信道响应于第一通信信道具有其所有未完成的存储器事务到公共源地址组和作为源地址组的源地址页和第一存储器转移请求的源地址页。

9. 发明授权

US09128925B2 System and method for direct memory access buffer utilization by setting DMA controller with plurality of arbitration weights associated with different DMA engines 有权
标题翻译：通过设置具有与不同DMA引擎相关联的多个仲裁权重的DMA控制器来直接存储器访问缓冲器利用的系统和方法
公开(公告)号：US09128925B2
公开(公告)日：2015-09-08
申请号：US13454505
申请日：2012-04-24
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： G06F13/14 , G06F13/28
CPC分类号： G06F13/28
摘要： A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.
摘要翻译： DMA控制器根据数据段已经存储在缓冲区的时间长度，将缓冲区的空间分配给不同的DMA引擎。该分配确保与经历较高拥塞的目的地相关联的DMA引擎将被分配比经历较低拥塞的目的地更少的缓冲区空间。此外，DMA控制器能够适应转移目的地处的变化的拥塞状况。

10. 发明授权

US09054998B2 System and method for maintaining packet order in an ordered data stream 有权
标题翻译：用于在有序数据流中维护分组顺序的系统和方法
公开(公告)号：US09054998B2
公开(公告)日：2015-06-09
申请号：US13760109
申请日：2013-02-06
申请人： Tommi M. Jokinen , David B. Kramer , Kun Xu
发明人： Tommi M. Jokinen , David B. Kramer , Kun Xu
IPC分类号： H04L12/861 , H04L12/863
CPC分类号： H04L47/62
摘要： A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.
摘要翻译：源处理器可以在分组通信之前将数据流的每个分组划分成多个分段，从而允许以更小的分组发送分组。源处理器可以对于给定数据流并发地处理两个或更多个分组的分段，并且在每个分段报头中提供适当的上下文信息，以有助于顺序发送和接收由各个分段表示的分组。类似地，目的地处理器可以从源处理器接收用于有序数据流的分组分段分组，并且可以基于每个分段报头中的上下文信息来分配不同的上下文。当针对特定分组接收到最后一个分段时，特定分组的上下文被关闭，并且分组的描述符被发送到队列。传送数据包的最后一个段的顺序维护数据包之间的顺序。

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