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1. 发明授权

US5821146A Method of fabricating FET or CMOS transistors using MeV implantation 失效
标题翻译：使用MeV植入制造FET或CMOS晶体管的方法
公开(公告)号：US5821146A
公开(公告)日：1998-10-13
申请号：US479880
申请日：1995-06-07
申请人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Fred Hause
发明人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Fred Hause
IPC分类号： H01L21/266 , H01L21/8238 , H01L27/092 , H01L21/336
CPC分类号： H01L21/266 , H01L21/823814 , H01L27/0925
摘要： A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.
摘要翻译：一种制造具有LDD区域的方法，其中通过以1MeV和更大的能量注入离子通过光致抗蚀剂层形成源极和漏极区域，并且在除去氧化物层之后通过低能离子注入形成LDD区域从有源区和门。在第二实施例中，源极和漏极区域通过离子注入形成为没有光致抗蚀剂层，并且在从有源区域和栅极去除氧化物层之后，通过低能离子注入形成LDD区域。

2. 发明授权

US5554562A Advanced isolation scheme for deep submicron technology 失效
公开(公告)号：US5554562A
公开(公告)日：1996-09-10
申请号：US417572
申请日：1995-04-06
申请人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Yowjuang W. Liu , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.

3. 发明授权

US5643825A Integrated circuit isolation process 失效
标题翻译：集成电路隔离过程
公开(公告)号：US5643825A
公开(公告)日：1997-07-01
申请号：US366053
申请日：1994-12-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/762
摘要： An improved process is provided for forming field dielectric in lieu of local oxidation process often referred to as the "LOCOS" process. The improved process utilizes blanket formation of first and second dielectrics across an entire semiconductor substrate. In a subsequent step, both first and second dielectrics are selectively removed in areas overlying active regions. The first and second dielectrics are formed using a combination of thermal growth and/or chemical deposition. The resulting field dielectric structure is relatively thin, yet demonstrates superior dielectric properties. Blanket formation followed by select removal ensures a fine-line demarcation between field and active regions and substantially eliminates encroachment problems normally associated with conventional LOCOS. Additionally, the thin field dielectric structure can be formed with rounded or reflowed corners to avoid step coverage problems for subsequently placed conductive elements.
摘要翻译：提供了用于形成场电介质以代替通常称为“LOCOS”工艺的局部氧化工艺的改进方法。改进的方法利用穿过整个半导体衬底的第一和第二电介质的覆盖层形成。在随后的步骤中，第一和第二电介质在覆盖有源区域的区域中被选择性地去除。使用热生长和/或化学沉积的组合形成第一和第二电介质。所得到的场介电结构相对较薄，但表现出优异的介电性能。毯子形成，然后选择移除确保场和活动区域之间的细线划分，并且基本上消除通常与常规LOCOS相关联的侵入问题。此外，薄场电介质结构可以形成为圆形或回流角，以避免随后放置的导电元件的步骤覆盖问题。

4. 发明授权

US5950097A Advanced isolation scheme for deep submicron technology 失效
标题翻译：深亚微米技术的先进隔离方案
公开(公告)号：US5950097A
公开(公告)日：1999-09-07
申请号：US698828
申请日：1996-08-16
申请人： Kuang-Yeh Chang , Yowjuang William Liu , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Yowjuang William Liu , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/20 , H01L21/762 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L21/76294
摘要： An oxide layer is thermally grown over a semiconductor body, and openings are etched in the oxide layer to expose portions of the surface of the semiconductor body. Then, epitaxial regions are grown from the semiconductor body into the openings in the oxide layer, which epitaxial regions will eventually become the active regions of devices.
摘要翻译：氧化物层在半导体本体上热生长，并且在氧化物层中蚀刻开口以暴露半导体本体的表面的部分。然后，外延区域从半导体本体生长到氧化物层中的开口中，这些外延区域最终将成为器件的有源区域。

5. 发明授权

US5811347A Nitrogenated trench liner for improved shallow trench isolation 失效
标题翻译：氮化沟槽衬垫，用于改善浅沟槽隔离
公开(公告)号：US5811347A
公开(公告)日：1998-09-22
申请号：US641028
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/314 , H01L21/318 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/3185 , H01L21/76224 , Y10S148/05
摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.sub.2 trench liner and subsequently implanting the SiO.sub.2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬里中。通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

6. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

7. 发明授权

US5962914A Reduced bird's beak field oxidation process using nitrogen implanted into active region 有权
公开(公告)号：US5962914A
公开(公告)日：1999-10-05
申请号：US168761
申请日：1998-10-08
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L24/36
CPC分类号： H01L21/76213
摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

8. 发明授权

US5937310A Reduced bird's beak field oxidation process using nitrogen implanted into active region 失效
标题翻译：使用植入活动区域的氮减少鸟的喙场氧化过程
公开(公告)号：US5937310A
公开(公告)日：1999-08-10
申请号：US639758
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/265 , H01L21/316 , H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02299 , H01L21/26506 , H01L21/31662 , H01L21/32 , H01L21/76213 , Y10S438/981
摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.
摘要翻译：在不使用氮化硅的情况下形成自对准场氧化物隔离结构的方法。该方法包括在半导体衬底的上表面上形成电介质。半导体衬底的上表面包括相互横向相邻的有源区和隔离区。在植入电介质的顶部上构图光致抗蚀剂层，以在有源区域上暴露植入电介质的区域。然后通过植入电介质将氮注入有源区。氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

9. 发明授权

US5512506A Lightly doped drain profile optimization with high energy implants 失效
标题翻译：用高能量植入物进行轻掺杂漏极分布优化
公开(公告)号：US5512506A
公开(公告)日：1996-04-30
申请号：US417568
申请日：1995-04-06
申请人： Kuang-Yeh Chang , Mark I. Gardner , Frederick N. Hause
发明人： Kuang-Yeh Chang , Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/336 , H01L29/78 , H01L21/266
CPC分类号： H01L29/6659 , H01L29/7833
摘要： After growth of a thin oxide on a silicon semiconductor body, and formation of a gate thereover, a blanket layer of oxide is deposited over the resulting structure, this oxide layer having, as measured from the surface of the silicon body, relatively thick regions adjacent the sides of the gate and relatively thin regions extending therefrom. Upon implant of ions, the relatively thick regions block ions from passing therethrough into the semiconductor body, while the relatively thin regions allow passage of ions therethrough into the body. After drivein of the ions, the thick layer of oxide is isotopically etched to take a substantially uniform layer therefrom over the entire surface of the thick oxide layer, so that the thick regions thereof are reduced in width. Upon a subsequent ion implant step, the thick regions, now reduced in width from the sides of the gate, block passage of ions therethrough, while the thin regions allow ions therethrough into the silicon body. This process may be continued as chosen to from a desired source and drain profile.
摘要翻译：在硅半导体本体上生长薄氧化物并在其上形成栅极之后，在所得结构上沉积氧化物覆盖层，该氧化物层具有从硅体表面测量的较厚的相邻区域门的侧面和从其延伸的相对薄的区域。在离子注入时，相对较厚的区域阻止离子通过其进入半导体本体，而较薄的区域允许离子通过其进入体内。在离子的驱动之后，厚厚的氧化物层被同位素蚀刻以在厚氧化物层的整个表面上从其中获得基本均匀的层，使得其厚的区域的宽度减小。在随后的离子注入步骤中，现在从栅极的侧面减小宽度的厚区域阻止离子通过其中，而薄区域允许离子通过其进入硅体。该过程可以根据期望的源和漏极曲线选择继续。

10. 发明授权

US5904539A Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties 失效
标题翻译：半导体沟槽隔离工艺导致硅台面具有增强的机械和电学性能
公开(公告)号：US5904539A
公开(公告)日：1999-05-18
申请号：US619004
申请日：1996-03-21
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

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