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1. 发明授权

US07176111B2 Method for depositing polycrystalline SiGe suitable for micromachining and devices obtained thereof 有权
标题翻译：用于沉积适合微加工的多晶SiGe的方法及其获得的器件
公开(公告)号：US07176111B2
公开(公告)日：2007-02-13
申请号：US10263623
申请日：2002-10-03
申请人： Kris Baert , Matty Caymax , Cristina Rusu , Sherif Sedky , Ann Witvrouw
发明人： Kris Baert , Matty Caymax , Cristina Rusu , Sherif Sedky , Ann Witvrouw
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L31/1804 , B81C1/00666 , B81C2201/0164 , B81C2201/017 , C23C16/22 , G01J5/20 , H01L31/09 , Y02E10/547 , Y02P70/521
摘要： Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1−x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.
摘要翻译：获得沉积的多晶和低应力SiGe层的方法和装置。这些层可以用于微机电系统（MEMS）装置或微加工结构中。分析影响多晶层中的应力的不同参数。参数包括但不限于：沉积温度; 半导体的浓度（例如，硅和锗在Si 1 x 1-x层中的浓度，x是浓度参数）; 掺杂剂的浓度（例如硼或磷的浓度）; 压力量; 并使用等离子体。取决于多晶SiGe生长的特定环境，可以使用不同的参数值。

2. 发明授权

US08383441B2 Method for manufacturing a micromachined device and the micromachined device made thereof 有权
标题翻译：微加工装置的制造方法及其制造的微加工装置
公开(公告)号：US08383441B2
公开(公告)日：2013-02-26
申请号：US13010923
申请日：2011-01-21
申请人： Joumana El Rifai , Ann Witvrouw , Ahmed Abdel Aziz , Sherif Sedky
发明人： Joumana El Rifai , Ann Witvrouw , Ahmed Abdel Aziz , Sherif Sedky
IPC分类号： H01L21/00
CPC分类号： B81C1/00666 , B81C1/00698
摘要： Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence.
摘要翻译：公开了制造微加工装置和所获得的装置的方法。在一个实施例中，该方法包括提供包括非晶半导体材料的结构层，在结构层的第一部分上形成屏蔽层，并留下暴露的结构层的第二部分，并且使用第一注量使第二部分退火。该方法还包括去除屏蔽层，并且使用小于第一注量的一半的第二注量来退火第一部分和第二部分。在一个实施例中，该器件包括衬底层，形成在衬底层上的下层，以及仅在下层的一部分上形成的牺牲层。该装置还包括与下面的层接触的结构层，并且包括使用第一注量退火的第一区域和使用第二能量密度退火的第二区域。

3. 发明申请

US20110180886A1 Method for Manufacturing a Micromachined Device and the Micromachined Device Made Thereof 有权
标题翻译：微加工装置的制造方法及其制造的微加工装置
公开(公告)号：US20110180886A1
公开(公告)日：2011-07-28
申请号：US13010923
申请日：2011-01-21
申请人： Joumana El Rifai , Ann Witvrouw , Ahmed Kamal Said Abdel Aziz , Sherif Sedky
发明人： Joumana El Rifai , Ann Witvrouw , Ahmed Kamal Said Abdel Aziz , Sherif Sedky
IPC分类号： H01L29/84 , H01L21/477
CPC分类号： B81C1/00666 , B81C1/00698
摘要： Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence.
摘要翻译：公开了制造微加工装置和所获得的装置的方法。在一个实施例中，该方法包括提供包括非晶半导体材料的结构层，在结构层的第一部分上形成屏蔽层，并留下暴露的结构层的第二部分，并且使用第一注量使第二部分退火。该方法还包括去除屏蔽层，并且使用小于第一注量的一半的第二注量来退火第一部分和第二部分。在一个实施例中，该器件包括衬底层，形成在衬底层上的下层，以及仅在下层的一部分上形成的牺牲层。该装置还包括与下面的层接触的结构层，并且包括使用第一注量退火的第一区域和使用第二能量密度退火的第二区域。

4. 发明申请

US20100032812A1 Method for forming silicon germanium layers at low temperatures, layers formed therewith and structures comprising such layers 审中-公开
标题翻译：在低温下形成硅锗层的方法，与其形成的层以及包括这些层的结构
公开(公告)号：US20100032812A1
公开(公告)日：2010-02-11
申请号：US11643235
申请日：2006-12-21
申请人： Sherif Sedky , Ann Witvrouw
发明人： Sherif Sedky , Ann Witvrouw
IPC分类号： H01L29/161 , H01L21/20
CPC分类号： B81C1/00666 , B81C2201/0169
摘要： A method is provided for controlling the average stress and the strain gradient in structural silicon germanium layers as used in micromachined devices. The method comprises depositing a single silicon germanium layer on a substrate and annealing a predetermined part of the deposited silicon germanium layer. The process parameters of the depositing and/or annealing steps are selected such that a predetermined average stress and a predetermined strain gradient are obtained in the predetermined part of the silicon germanium layer. Preferably a plasma assisted deposition technique is used for depositing the silicon germanium layer, and a pulsed excimer laser is used for local annealing, with a limited thermal penetration depth. Structural silicon germanium layers for surface micromachined structures can be formed at temperatures substantially below 400° C., which offers the possibility of post-processing micromachined structures on top of a substrate comprising electronic circuitry such as CMOS circuitry. Such structural silicon germanium layers may be also be formed at temperatures not exceeding 210° C., which allows the integration of silicon germanium based micromachined structures on substrates such as polymer films.
摘要翻译：提供了一种用于控制在微加工装置中使用的结构硅锗层中的平均应力和应变梯度的方法。该方法包括在衬底上沉积单个硅锗层并退火沉积的硅锗层的预定部分。选择沉积和/或退火步骤的工艺参数，使得在硅锗层的预定部分中获得预定的平均应力和预定的应变梯度。优选地，等离子体辅助沉积技术用于沉积硅锗层，并且将脉冲准分子激光器用于具有有限的热穿透深度的局部退火。用于表面微加工结构的结构硅锗层可以在基本上低于400℃的温度下形成，这提供了在包括诸如CMOS电路的电子电路的衬底之上的后处理微机械加工结构的可能性。这种结构硅锗层也可以在不超过210℃的温度下形成，这允许将硅锗微加工结构集成在诸如聚合物膜的基底上。

5. 发明授权

US07235281B2 Method for the closure of openings in a film 有权
标题翻译：用于封闭薄膜中开口的方法
公开(公告)号：US07235281B2
公开(公告)日：2007-06-26
申请号：US10745281
申请日：2003-12-22
申请人： Cristina Rusu , Ann Witvrouw
发明人： Cristina Rusu , Ann Witvrouw
IPC分类号： C23C16/00
CPC分类号： B81C1/00293 , B81C2203/0136 , B81C2203/0145 , H01L21/7682
摘要： A method is described for closing openings in a film, for example, in microelectronic process technology, whereby substantially no deposition material passes through the openings, which can be important if fragile micro devices are positioned under the openings. The closure of these openings can cause an underlying cavity to be hermetically sealed, in which an object can be located. In particular the method provides a way for hermetically sealing cavities under controlled atmosphere and pressure in the encapsulation and sealing processes of cavities comprising fragile content. The cavities may comprise for example Micro Electro Mechanical Systems (MEMS). The method may be used for encapsulating devices which may require a controlled atmosphere and pressure encapsulation such as micro accelerometers, micro gyroscopes, micro tubes, vibration micro sensors, micro mirrors, micro mechanical resonators or “resonant strain gauges”, micro mechanical filters, micro switches, micro electrical circuits, micro relays, Integrated Circuits with air gaps etc.
摘要翻译：描述了一种用于封闭薄膜中的开口的方法，例如在微电子工艺技术中，从而基本上没有沉积材料穿过开口，如果脆性微器件位于开口下方，这可能是重要的。这些开口的封闭可以使下面的空腔被气密地密封，物体可以位于其中。特别地，该方法提供了一种在包含脆弱内容的空腔的包封和密封过程中在受控气氛和压力下气密密封腔的方法。空腔可以包括例如微机电系统（MEMS）。该方法可以用于可能需要受控气氛和压力封装的封装装置，例如微加速度计，微陀螺仪，微管，振动微传感器，微反射镜，微机械谐振器或“共振应变计”，微机械滤波器，微型开关，微电路，微型继电器，带气隙的集成电路等

6. 发明申请

US20100210073A1 Method for Encapsulating a Device in a Microcavity 审中-公开
标题翻译：在微腔中封装器件的方法
公开(公告)号：US20100210073A1
公开(公告)日：2010-08-19
申请号：US12772976
申请日：2010-05-03
申请人： Ann Witvrouw , Chris Van Hoof , Jan Fransaer , Jean-Pierre Celis , Raquel Consuelo Hellin Rico , Anthony Joseph Muscat
发明人： Ann Witvrouw , Chris Van Hoof , Jan Fransaer , Jean-Pierre Celis , Raquel Consuelo Hellin Rico , Anthony Joseph Muscat
IPC分类号： H01L21/56
CPC分类号： B81C1/00293 , B81C2203/0145
摘要： Manufacturing a semiconductor device involves forming (200) a sacrificial layer where a micro cavity is to be located, forming (210) a metal layer of thickness greater than 1 micron over the sacrificial layer, forming (220) a porous layer from the metal layer, the porous layer having pores of length greater than ten times their breadth, and having a breadth in the range 10 nm-500 nanometers. The pores can be created by anodising, electrodeposition or dealloying. Then the sacrificial layer can be removed (230) through the porous layer, to form the micro cavity, and pores can be sealed (240). Encapsulating MEMS devices with a porous layer can reduce costs by avoiding using photolithography for shaping the access holes since the sacrificial layer is removed through the porous membrane.
摘要翻译：制造半导体器件涉及形成（200）牺牲层，其中微空腔将被定位，在牺牲层上形成（210）厚度大于1微米的金属层，从金属层形成（220）多孔层所述多孔层具有长度大于其宽度的十倍的孔，并且其宽度在10nm-500纳米的范围内。孔可以通过阳极氧化，电沉积或脱铝合金来形成。然后可以通过多孔层去除牺牲层（230），以形成微腔，并且可以密封孔（240）。使用多孔层封装MEMS器件可以通过避免使用光刻来成形入口孔来降低成本，因为牺牲层通过多孔膜去除。

7. 发明申请

US20100062224A1 METHOD FOR MANUFACTURING A MICROMACHINED DEVICE 审中-公开
标题翻译：制造微型设备的方法
公开(公告)号：US20100062224A1
公开(公告)日：2010-03-11
申请号：US12447574
申请日：2007-10-31
申请人： Ann Witvrouw , Luc Haspeslagh
发明人： Ann Witvrouw , Luc Haspeslagh
IPC分类号： B32B3/00 , B32B38/10 , H01B13/00 , C25F3/02
CPC分类号： H01L21/324 , B81C1/00246 , B81C2203/0735 , Y10T428/24612
摘要： The present invention provides a method for manufacturing micromachined devices on a substrate (10) comprising electrical circuitry, the micromachined devices comprising at least one micromachined structure, without affecting the underlying electrical circuitry. The method comprises providing a protection layer (15) on the substrate (10); providing on the protection layer (15) a plurality of patterned layers for forming the at least one micromachined structure, the plurality of patterned layers comprising at least one sacrificial layer (18); and thereafter removing at least a portion of the sacrificial layer (18) to release the at least one micromachined structure. The method furthermore comprises, before providing the protection layer (15), annealing the substrate (10) at a temperature higher than a highest temperature used during manufacturing of the micromachined device, annealing being for preventing gas formation underneath the protection layer (15) during subsequent manufacturing steps. The present invention also provides a micromachined device obtained by the method according to embodiments of the present invention.
摘要翻译：本发明提供了一种用于在包括电路的衬底（10）上制造微加工器件的方法，所述微加工器件包括至少一个微加工结构，而不影响下面的电路。该方法包括在衬底（10）上提供保护层（15）。在所述保护层（15）上设置多个用于形成所述至少一个微机械加工结构的图案化层，所述多个图案化层包括至少一个牺牲层（18）; 然后去除所述牺牲层（18）的至少一部分以释放所述至少一个微加工结构。该方法还包括在提供保护层（15）之前，在高于在微机械加工装置的制造期间使用的最高温度的温度下退火衬底（10），用于在保护层（15）的下方防止形成气体的退火后续制造步骤。本发明还提供了通过根据本发明的实施例的方法获得的微加工装置。

8. 发明授权

US06740542B2 Method for producing micromachined devices and devices obtained thereof 失效
标题翻译：用于制造微加工装置的方法及其获得的装置
公开(公告)号：US06740542B2
公开(公告)日：2004-05-25
申请号：US09973277
申请日：2001-10-09
申请人： Ann Witvrouw , Atze de Vries , Piet De Moor , Luc Haspeslagh , Brigitte Parmentier , Agnes Verbist , Constantine Anagnostopoulos
发明人： Ann Witvrouw , Atze de Vries , Piet De Moor , Luc Haspeslagh , Brigitte Parmentier , Agnes Verbist , Constantine Anagnostopoulos
IPC分类号： H01L2144
CPC分类号： B81C1/00404 , H01L29/045 , Y10S438/973
摘要： The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.
摘要翻译：本发明涉及一种用于生产用于微机电系统（MEMS）的微加工装置的方法，包括以下步骤：提供晶片，以及从所述晶片处理至少一个微加工装置，所述至少一个微加工装置包括至少一个细长的开口和/或腔具有纵向轴线，使得所述纵向轴线与沿着晶片的前平面和解理平面的相交的方向成一定角度，所述解理平面被定义为沿晶片切割的平面最有可能发生。

9. 发明申请

US20110180943A1 Thin Film Wafer Level Package 有权
标题翻译：薄膜晶圆级封装
公开(公告)号：US20110180943A1
公开(公告)日：2011-07-28
申请号：US13012275
申请日：2011-01-24
申请人： Gert Claes , Ann Witvrouw
发明人： Gert Claes , Ann Witvrouw
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： B81B7/0077 , B81B2207/015 , B81C2203/0136 , B81C2203/0163 , B81C2203/0714 , B81C2203/0735
摘要： Anchor designs for thin film packages are disclosed that, in a preferred embodiment are a combination of SiGe-filled trenches and Si-oxide-filled spacing. Depending on the release process, additional manufacturing process steps are performed in order to obtain a desired mechanical strength. For aggressive release processes, additional soft sputter etch and a Ti—TiN interlayer in the anchor region may be added. The ratio of the total SiGe—SiGe anchor area to the SiO2—SiGe anchor area determines the mechanical strength of the anchor. If this ratio is larger than 1, the thin film package reaches the MIL-standard requirements.
摘要翻译：公开了薄膜封装的锚定设计，在优选实施例中是填充SiGe的沟槽和填充Si氧化物的间隔的组合。取决于释放过程，进行附加的制造工艺步骤以获得期望的机械强度。对于侵蚀性释放过程，可以添加另外的软溅射蚀刻和锚定区域中的Ti-TiN中间层。总SiGe-SiGe锚定面积与SiO2-SiGe锚定面积的比率决定了锚的机械强度。如果该比例大于1，薄膜封装达到MIL标准要求。

10. 发明申请

US20050037598A1 Method for producing polycrystalline silicon germanium and suitable for micromachining 审中-公开
标题翻译：生产多晶硅锗的方法，适用于微加工
公开(公告)号：US20050037598A1
公开(公告)日：2005-02-17
申请号：US10835082
申请日：2004-04-28
申请人： Ann Witvrouw
发明人： Ann Witvrouw
IPC分类号： C23C16/02 , C23C16/30 , C23C16/50 , H01L21/20 , H01L21/205
CPC分类号： C23C16/0272 , C23C16/30 , C23C16/50 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/02579 , H01L21/0262
摘要： The invention relates to methods for preparing as-deposited, low-stress and low resistivity polycrystalline silicon-germanium layers and semiconductor devices utilizing the silicon-germanium layers. These layers can be used in Micro Electro-Mechanical Systems (MEMS) devices or micro-machined structures.
摘要翻译：本发明涉及用于制备沉积的，低应力和低电阻率的多晶硅 - 锗层以及利用硅 - 锗层的半导体器件的方法。这些层可用于微机电系统（MEMS）装置或微加工结构。

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