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1. 发明授权

US4528634A Bit pattern generator 失效
标题翻译：位模式发生器
公开(公告)号：US4528634A
公开(公告)日：1985-07-09
申请号：US433405
申请日：1982-10-08
申请人： Kozo Nakahata , Ikuo Kawaguchi , Kazuo Yamaguchi
发明人： Kozo Nakahata , Ikuo Kawaguchi , Kazuo Yamaguchi
IPC分类号： G01B21/20 , G06F1/03 , G06T7/00 , G06T11/20 , G09G5/42 , H01L21/027 , H01L21/30 , H01L21/66 , G06F15/40
CPC分类号： H01L21/30 , G06F1/03 , G09G5/42
摘要： A bit pattern generator includes two memories which are provided for storing a bit pattern for a scanning line produced from design data. When a bit pattern is created and stored in one of the memories, the previously created and stored bit pattern is read out from the other memory. For the creation of each bit pattern, a scanning line is divided into a plurality of bytes. Model patterns of bit patterns existing in the respective bytes are stored in a ROM. From the combination of start point and end point addresses specifying the byte positions and the ROM addresses, a ROM address for each byte is logically determined so that any model patterns in the ROM are sequentially stored in the first mentioned memories.
摘要翻译：位模式发生器包括两个存储器，用于存储由设计数据产生的扫描线的位模式。当一个位模式被创建并存储在一个存储器中时，先前创建和存储的位模式从另一个存储器读出。为了创建每个位模式，扫描线被分成多个字节。存储在各个字节中的位模式的模型模式存储在ROM中。根据指定字节位置和ROM地址的起始点和终点地址的组合，逻辑地确定每个字节的ROM地址，使得ROM中的任何模型模式被顺序地存储在首先提到的存储器中。

2. 发明授权

US5325506A Method of changing the track and recording data 失效
标题翻译：更改轨道和记录数据的方法
公开(公告)号：US5325506A
公开(公告)日：1994-06-28
申请号：US948513
申请日：1992-09-22
申请人： Mamoru Tohchi , Akira Kurano , Hisaharu Takeuchi , Yukihisa Kashima , Ikuo Kawaguchi
发明人： Mamoru Tohchi , Akira Kurano , Hisaharu Takeuchi , Yukihisa Kashima , Ikuo Kawaguchi
IPC分类号： G06F3/06 , G11B19/02 , G11B19/20 , G11B20/10 , G11B27/10 , G11B15/12
CPC分类号： G11B19/20 , G06F3/0601 , G11B19/02 , G11B27/105 , G06F2003/0692
摘要： An external memory device subsystem and a data recording device, which issue a command specifying previously a plurality of tracks in a rotary type memory device prior to a read or write instruction issued from the data processing unit of higher rank to the rotary type memory device through a control unit; select continuously the plurality of tracks previously specified, at executing a read or write command after the execution of the command; and in this way can read/write continuously without wait time for rotation a plurality of tracks distant from each other within the same cylinder.
摘要翻译：一种外部存储器件子系统和数据记录装置，其在从旋转式存储装置的较高等级的数据处理单元发出的读取或写入指令之前发出在旋转型存储装置中预先指定多个轨迹的命令，一个控制单元; 在执行命令后执行读或写命令，连续选择先前指定的多个轨道; 并且以这种方式可以连续读/写，而无需等待时间旋转在同一气缸内彼此远离的多个轨道。

3. 发明授权

US5179684A Method of changing the track and recording data 失效
标题翻译：更改跟踪和记录数据的方法
公开(公告)号：US5179684A
公开(公告)日：1993-01-12
申请号：US394537
申请日：1989-08-16
申请人： Mamoru Tohchi , Akira Kurano , Hisaharu Takeuchi , Yukihisa Kashima , Ikuo Kawaguchi
发明人： Mamoru Tohchi , Akira Kurano , Hisaharu Takeuchi , Yukihisa Kashima , Ikuo Kawaguchi
IPC分类号： G06F3/06 , G11B19/02 , G11B19/20 , G11B20/10 , G11B27/10
CPC分类号： G11B19/20 , G06F3/0601 , G11B19/02 , G11B27/105 , G06F2003/0692
摘要： An external memory device subsystem and a data recording device, which issue a command specifying a plurality of tracks (surfaces) in a rotary type memory device prior to a read or write instruction being issued from the data processing unit of higher rank to the rotary type memory device through a control unit; selects sequentially the plurality of individual tracks (surfaces) previously specified when executing a read or write command after the receipt of the command; and in this way can read/write continuously without wait time interruptions when data is discontinuous.
摘要翻译：一种外部存储器件子系统和数据记录装置，其在从具有更高级别的数据处理单元向旋转型发出读取或写入指令之前发出指定旋转型存储器件中的多个轨道（表面）的命令存储设备通过控制单元; 在接收到命令之后执行读或写命令时，依次选择预先指定的多个单独的轨道（曲面）; 并且以这种方式可以在数据不连续时连续读/写等待时间中断。

4. 发明授权

US4193086A Convergence detecting device for color picture tube 失效
标题翻译：彩色显像管收敛检测装置
公开(公告)号：US4193086A
公开(公告)日：1980-03-11
申请号：US871253
申请日：1978-01-23
申请人： Ikuo Kawaguchi
发明人： Ikuo Kawaguchi
IPC分类号： H01J9/42 , H01J9/44 , H04N17/04 , H04N9/62
CPC分类号： H04N17/04
摘要： A pattern signal for sequentially displaying crisscross patterns of three primary colors of red, green and blue is supplied to a color picture tube. Two television cameras pick up the pattern images displayed on the color picture tube through a 1:1 half mirror. The line scanning directions of the first and second television cameras are horizontal and vertical respectively with respect to the CRT display screen. The aspect ratio of the first television camera is selected to be equal to that of the CRT display screen, and the aspect ratio of the second television camera is selected to be equal to the reciprocal of that of the CRT display screen. The image output signals of these two television cameras are selectively supplied to an image processing circuit by a change-over unit. In this image processing circuit, a counter counts the time-related positions of peak values appearing within a specified line scanning period in the image signals supplied through the change-over unit. The degree of convergence is detected by detecting the differences between the time-related peak value positions in the red, green and blue patterns.
摘要翻译：用于顺序显示红色，绿色和蓝色的三原色十字形图案信号被提供给彩色显像管。两台电视摄像机通过1：1半反射镜拾取彩色显像管上显示的图案图像。第一和第二电视摄像机的行扫描方向分别相对于CRT显示屏水平和垂直。选择第一电视摄像机的纵横比等于CRT显示屏的宽高比，并且选择第二电视摄像机的纵横比等于CRT显示屏的纵横比。这两个电视摄像机的图像输出信号通过转换单元选择性地提供给图像处理电路。在该图像处理电路中，计数器对通过转换单元提供的图像信号中在指定行扫描期间出现的峰值的时间相关位置进行计数。通过检测红色，绿色和蓝色图案中的时间相关峰值位置之间的差异来检测收敛度。

5. 发明授权

US4905183A Pattern generator having plural pattern generating units executing instructions in parallel 失效
标题翻译：具有并行执行指令的多个图形生成单元的图案生成单元
公开(公告)号：US4905183A
公开(公告)日：1990-02-27
申请号：US78993
申请日：1987-07-29
申请人： Ikuo Kawaguchi , Shuji Kikuchi , Chisato Hamabe
发明人： Ikuo Kawaguchi , Shuji Kikuchi , Chisato Hamabe
IPC分类号： G01R31/319 , G06F7/544
CPC分类号： G06F7/544 , G01R31/31921
摘要： A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.
摘要翻译：模式发生器允许高速输出图形并具有适用于产生存储器IC的测试图案的操作功能。虽然迄今为止已知通过操作多个图案发生器来提高操作速度，对于哪些图案从先前存储图案的存储器生成的图案并行地，不可能并行地操作具有操作功能的图案生成器。通过这样一种方法，通过这种方式，对每个模式发生器和操作处理指令分配操作处理指令的执行顺序，并且通过具有操作功能的模式发生器允许高速生成模式。具体地，操作处理指令被分组和重新排列，使得所有模式发生器并行地执行指令。

6. 发明授权

US4788684A Memory test apparatus 失效
标题翻译：记忆体测试仪
公开(公告)号：US4788684A
公开(公告)日：1988-11-29
申请号：US895846
申请日：1986-08-12
申请人： Ikuo Kawaguchi , Yoshihiko Hayashi
发明人： Ikuo Kawaguchi , Yoshihiko Hayashi
IPC分类号： G11C29/56 , G06F11/26
CPC分类号： G11C29/56
摘要： A memory test apparatus for testing a high-performance memory having two or more memory functions, including a pattern generator for generating an algorithmic pattern to be inputted to a first memory block of a memory under test having at least two memory blocks, an auxiliary pattern generator for storing an output from the algorithmic pattern generator and for outputting an expected value to a second memory block of the memory under test at a preset timing based on the stored output, a comparator for comparing outputs from the first and second memory blocks with expected values for the memory blocks, and a memory for storing an output from the comparator. Since the algorithmic pattern generator and the auxiliary pattern generator are included, the test apparatus has such an affect that even if the first and second memory blocks of the memory under test operate asynchronously, the data transfer function therebetween and the performance related to the operation timing can be tested, thus providing a highly precise memory test apparatus.
摘要翻译：一种用于测试具有两个或多个存储器功能的高性能存储器的存储器测试装置，包括用于产生要输入到具有至少两个存储器块的被测存储器的第一存储器块的算法模式的模式发生器，辅助模式发生器，用于存储来自算法模式发生器的输出，并且用于基于存储的输出在预设定时将预期值输出到被测存储器的第二存储器块;比较器，用于将来自第一和第二存储器块的输出与预期的存储器块的值，以及用于存储来自比较器的输出的存储器。由于包含算法模式生成器和辅助模式生成器，所以测试装置具有这样的影响：即使被测存储器的第一和第二存储器块异步操作，其间的数据传递功能和与操作时序相关的性能可以进行测试，从而提供高精度的记忆测试装置。

7. 发明授权

US5811877A Semiconductor device structure 失效
标题翻译：半导体器件结构
公开(公告)号：US5811877A
公开(公告)日：1998-09-22
申请号：US829144
申请日：1997-03-31
申请人： Ichiro Miyano , Ikuo Kawaguchi , Kunio Matsumoto , Junichi Saeki , Tooru Yoshida , Naoya Kanda , Isamu Yoshida , Michifumi Kawai , Hideo Yamakura , Shigeharu Tsunoda , Ritsuro Orihashi , Masachika Masuda , Sueo Kawai
发明人： Ichiro Miyano , Ikuo Kawaguchi , Kunio Matsumoto , Junichi Saeki , Tooru Yoshida , Naoya Kanda , Isamu Yoshida , Michifumi Kawai , Hideo Yamakura , Shigeharu Tsunoda , Ritsuro Orihashi , Masachika Masuda , Sueo Kawai
IPC分类号： H01L21/50 , H01L21/56 , H01L21/70 , H01L23/28 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L23/48 , H01L25/18
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/4951 , H01L23/49568 , H01L25/105 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2225/1029 , H01L2225/1058 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01019 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/3025 , H01L2924/3511
摘要： An ultra-thin resin molded semiconductor device of high reliability with low cost and with easy repair at time of mounting. A plurality of these semiconductor devices are stacked to provide a semiconductor module which has a higher function than semiconductor devices in the same volume, and a card type module utilizing assembled by the stacked semiconductor module is provided. In manufacturing the semiconductor module, an extremely thin lead frame and an LSI chip are directly connected together, and the mirror surface of the LSI chip is exposed by using a low viscosity epoxy resin to have a thin molding. The mirror surface is grinded to have a further thin thickness of the whole structure of the semiconductor device. A part of the lead frame is formed as a reinforcing member, a heat radiation path, a light shielding part for shielding the LSI from harmful light beams, or a positioning base for mounting a substrate. The above ultra-thin resin molded semiconductor devices are interconnected together in a stacked layout to provide a stacked semiconductor module, and to provide a card type device having a higher function.
摘要翻译：一种超薄树脂模制半导体器件，可靠性高，成本低，安装时易于维修。多个这些半导体器件被堆叠以提供具有比相同体积的半导体器件更高功能的半导体模块，并且提供利用由堆叠的半导体模块组装的卡型模块。在制造半导体模块时，将极薄的引线框架和LSI芯片直接连接在一起，并且通过使用低粘度环氧树脂来暴露LSI芯片的镜面以具有薄的成型。研磨镜面以使半导体器件的整个结构具有更薄的厚度。引线框架的一部分形成为加强构件，散热路径，用于屏蔽LSI免受有害光束的遮光部分或用于安装基板的定位基座。上述超薄树脂模制半导体器件以堆叠的布局互连在一起以提供堆叠的半导体模块，并且提供具有更高功能的卡型设备。

8. 发明授权

US4759021A Test pattern generator 失效
标题翻译：测试模式发生器
公开(公告)号：US4759021A
公开(公告)日：1988-07-19
申请号：US920986
申请日：1986-09-30
申请人： Ikuo Kawaguchi , Masaaki Inadachi , Shuji Kikuchi
发明人： Ikuo Kawaguchi , Masaaki Inadachi , Shuji Kikuchi
IPC分类号： G01R31/319 , G06F11/22
CPC分类号： G01R31/31921
摘要： In a semiconductor testing device of LSI or the like, a high-speed small-capacity memory (50) is provided in addition to low-speed large-capacity memories (11.about.14) for interleave operation, and test patterns after a branch operation are previously stored in the memory (50). When test patterns are to be read in sequence the reading is performed from the low-speed large-capacity memories (11.about.14), and when branch is produced in the reading sequence the changing is performed to the high-speed small-capacity memory (50) and the test patterns are read from the high-speed small-capacity memory (50) until the reading from the low-speed large-capacity memories (11.about.14) again becomes possible. Thereby, the test patterns of a large number can be outputted without generating a dummy cycle.
摘要翻译： PCT No.PCT / JP86 / 00039 Sec。 371日期1986年9月30日第 102（e）1986年9月30日PCT申请人1986年1月31日PCT公布。出版物WO86 / 04686 日本1986年8月14日。在LSI等的半导体测试装置中，除了用于交错操作的低速大容量存储器（11差分14）之外还提供高速小容量存储器（50）并且分支操作之后的测试模式预先存储在存储器（50）中。当要读取测试图案时，从低速大容量存储器（11差分14）进行读取，并且当在读取顺序中产生分支时，对高速小容量存储器（50），并且从高速小容量存储器（50）读取测试图案，直到从低速大容量存储器（11差分14）读取再次变为可能。因此，可以输出大量的测试图案而不产生虚拟周期。

9. 发明授权

US4628509A Testing apparatus for redundant memory 失效
标题翻译：冗余存储器测试装置
公开(公告)号：US4628509A
公开(公告)日：1986-12-09
申请号：US609445
申请日：1984-05-11
申请人： Ikuo Kawaguchi
发明人： Ikuo Kawaguchi
IPC分类号： G06F11/20 , G11C29/00
CPC分类号： G11C29/72
摘要： Only that data which relates to detected failures of data stored in a memory under test is stored in a compressed data matrix of a small capacity which is determined by a predetermined number of redundant lines to be selected for remedy of the failures, and the selection of the redundant lines is effected during the execution of a test on the memory. Analysis leading to redundant line selection is effected on the data stored in this compressed matrix.
摘要翻译：只有与检测到的存储在待测存储器中的数据的检测到的故障有关的数据被存储在由预定数量的冗余线路确定的小容量的压缩数据矩阵中以被选择以补救故障，并且选择在对存储器执行测试期间实现冗余线路。导致冗余线路选择的分析对存储在该压缩矩阵中的数据进行。

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