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1. 发明授权

US5036486A Associative memory device 失效
标题翻译：关联存储器件
公开(公告)号：US5036486A
公开(公告)日：1991-07-30
申请号：US550156
申请日：1990-07-09
申请人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
发明人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
IPC分类号： G06F15/78 , G06F17/30 , G11C15/04
CPC分类号： G06F17/30982 , G11C15/04
摘要： In associative memory device, a search key is stored in the first storage element and a storage key is stored in the second storage elements, respectively via a first data bus. The search key is supplied to the comparator via a second data bus, and the storage key stored in the second storage element is supplied to the comparator. The comparator compares the search key with the storage key. When the storage key is consistent with the search key, the comparator delivers as the associative operation results a comparison consistency output signal to a priority encoder circuit which outputs code information having a limited bit length. This code information is transferred to CPU via a selector circuit. If the comparator delivers a comparison inconsistency output signal, this signal is directly passed to CPU via the priority encoder circuit, so that the contents of the first storage element is rewritten. The first and second storage elements are designated by an address signal and data is read or written via the first data bus, so that they are used as a usual memory device.
摘要翻译：在联想存储装置中，搜索关键字被存储在第一存储元件中，并且存储键分别通过第一数据总线存储在第二存储元件中。搜索键通过第二数据总线提供给比较器，存储在第二存储元件中的存储键提供给比较器。比较器将搜索键与存储键进行比较。当存储密钥与搜索关键字一致时，比较器输出，因为相关操作将比较一致性输出信号结果输出到输出具有有限位长度的代码信息的优先编码器电路。该代码信息通过选择电路传送到CPU。如果比较器提供比较不一致输出信号，则该信号通过优先编码器电路直接传递给CPU，从而重写第一存储元件的内容。第一和第二存储元件由地址信号指定，并且经由第一数据总线读取或写入数据，使得它们被用作通常的存储器件。

2. 发明授权

US5452451A System for plural-string search with a parallel collation of a first partition of each string followed by finite automata matching of second partitions 失效
标题翻译：用于多字符串搜索的系统，其中每个字符串的第一分区的并行排序以及第二分区的有限自动机匹配
公开(公告)号：US5452451A
公开(公告)日：1995-09-19
申请号：US349124
申请日：1994-12-01
申请人： Mitsuru Akizawa , Hisamitsu Kawaguchi , Kanji Kato , Atsushi Hatakeyama , Kouki Noguchi , Hiromichi Fujisawa
发明人： Mitsuru Akizawa , Hisamitsu Kawaguchi , Kanji Kato , Atsushi Hatakeyama , Kouki Noguchi , Hiromichi Fujisawa
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , Y10S707/99936 , Y10S707/99937
摘要： A parallel comparator for performing a parallel and high-speed processing for collation of partial character strings which are partially taken out of a plurality of character strings of interest to be searched out with a character string to be searched in which document data to be searched is arranged sequentially from a leading character, is provided in a front stage of an automaton executing device. Only when a part of the character string to be searched coincides with the partial character string set in the comparator, the collation of the remaining portion of the character string to be searched is performed by the automaton executing device. Also, it is possible to set "don't care" in which a character at any position in the partial character string is ignored at the time of comparison by the comparator and to set a negation condition in which the comparison by the comparator is made taking the negation of a character at any position in the partial character string.
摘要翻译：一种并行比较器，用于执行并行和高速处理，用于将要搜索的多个感兴趣的字符串部分地从要搜索的文档数据中搜索的字符串中部分取出的部分字符串对准，设置在自动机执行装置的前级中，从主角排列顺序排列。只有当要搜索的字符串的一部分与比较器中设置的部分字符串一致时，由自动机执行装置执行要搜索的字符串的剩余部分的核对。此外，可以设置在比较器比较时忽略部分字符串中的任何位置的字符的“无关心”，并且设置比较器进行比较的否定条件在部分字符串中的任何位置取一个字符。

3. 发明授权

US5101376A Integrated microprocessor with associative memory device 失效
标题翻译：集成微处理器与联想存储器件
公开(公告)号：US5101376A
公开(公告)日：1992-03-31
申请号：US690058
申请日：1991-04-23
申请人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
发明人： Kouki Noguchi , Mitsuru Akizawa , Kanji Kato
IPC分类号： G06F17/30 , G11C15/04
CPC分类号： G06F17/30982 , G11C15/04 , Y10S257/903
摘要： In associative memory device, a search key is stored in the first storage element and a storage key is stored in the second storage elements, respectively via a first data bus. The search key is supplied to the comparator via a second data bus, and the storage key stored in the second storage element is supplied to the comparator. The comparator compares the search key with the storage key. When the storage key is consistent with the search key, the comparator delivers as the associative operation results a comparison consistency output signal to a priority encoder circuit which outputs code information having a limited bit length. This code information is transferred to CPU via a selector circuit. If the comparator delivers a comparison inconsistency output signal, this signal is directly passed to CPU via the priority encoder circuit, so that the contents of the first storage element is rewritten. The first and second storage elements are designated by an address signal and data is read or written via the first data bus, so that they are used as a usual memory device.
摘要翻译：在联想存储装置中，搜索关键字被存储在第一存储元件中，并且存储键分别通过第一数据总线存储在第二存储元件中。搜索键通过第二数据总线提供给比较器，存储在第二存储元件中的存储键提供给比较器。比较器将搜索键与存储键进行比较。当存储密钥与搜索关键字一致时，比较器输出，因为相关操作将比较一致性输出信号结果输出到输出具有有限位长度的代码信息的优先编码器电路。该代码信息通过选择电路传送到CPU。如果比较器提供比较不一致输出信号，则该信号通过优先编码器电路直接传递给CPU，从而重写第一存储元件的内容。第一和第二存储元件由地址信号指定，并且经由第一数据总线读取或写入数据，使得它们被用作通常的存储器件。

4. 发明授权

US5497488A System for parallel string search with a function-directed parallel collation of a first partition of each string followed by matching of second partitions 失效
标题翻译：用于并行字符串搜索的系统，其中每个字符串的第一个分区的函数定向并行排序后跟第二个分区的匹配
公开(公告)号：US5497488A
公开(公告)日：1996-03-05
申请号：US402560
申请日：1995-03-13
申请人： Mitsuru Akizawa , Kouki Noguchi , Takehisa Hayashi , Kanji Kato , Hitoshi Matsushima
发明人： Mitsuru Akizawa , Kouki Noguchi , Takehisa Hayashi , Kanji Kato , Hitoshi Matsushima
IPC分类号： G06F7/02 , G06F17/30
CPC分类号： G06F17/30979 , G06F17/30982 , G06F17/30985 , G06F7/02 , G06F2207/025 , Y10S707/99936
摘要： A character string search arithmetic operation is performed at high speed with a small hardware scale processing module, such as a symbol string search module. The search module is connected to a CPU through address and data buses and includes a function definition section for defining a function of the apparatus in accordance with a command from the CPU, a data input/output section for receiving a symbol string to be searched through the data bus and for outputting the result of a search. A search processing section performs the search based on a function defined by the function definition section. A symbol string to be searched for, which is internally stored, is compared with the symbol string data input to the module's data input/output means. A condition holding section holds data indicative of an internal condition corresponding to the result of the search processing. Thereby, the CPU and the symbol string search module can perform the search at high speed.
摘要翻译：使用诸如符号串搜索模块的小型硬件规模处理模块来高速执行字符串搜索算术运算。搜索模块通过地址和数据总线连接到CPU，并且包括用于根据来自CPU的命令定义设备的功能的功能定义部分，用于接收要搜索的符号串的数据输入/输出部分数据总线并输出搜索结果。搜索处理部分基于由功能定义部分定义的功能来执行搜索。将内部存储的要搜索的符号串与输入到模块的数据输入/输出装置的符号串数据进行比较。条件保持部分保存指示与搜索处理结果相对应的内部条件的数据。因此，CPU和符号串搜索模块可以高速执行搜索。

5. 发明授权

US5398206A Semiconductor memory device with data error compensation 失效
标题翻译：具有数据误差补偿的半导体存储器件
公开(公告)号：US5398206A
公开(公告)日：1995-03-14
申请号：US654379
申请日：1991-02-12
申请人： Mitsuru Akizawa , Kazuhiko Iwasaki , Kouki Noguchi , Ryuuji Shibata , Noboru Yamaguchi
发明人： Mitsuru Akizawa , Kazuhiko Iwasaki , Kouki Noguchi , Ryuuji Shibata , Noboru Yamaguchi
IPC分类号： G11C29/00 , G11C29/24 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/24 , G11C29/74 , G11C29/76
摘要： A semiconductor memory device includes signal lines, a decoder for decoding an inputted address to output the decoded result to some of the signal lines, a matrixed memory array, a part of which being pre-specified as a compensated area, read out means for reading out data from memory cells in an area specified in accordance with a decode signal on the some signal line, a detector for detecting that the address is related with the compensated area from the decode signal on the some signal lines, the compensated area being pre-related with the some signal lines, and a fixed data outputting circuit for merging predetermined data into a predetermined part of the data read out from the memory cells in accordance with the detection signal to output the merged data. The fixed data outputting circuit is controlled by a control circuit in response to a merge control signal to output the data read out from the memory cells without the merging operation.
摘要翻译：半导体存储器件包括信号线，用于对输入的地址进行解码以将解码结果输出到某些信号线的解码器，其一部分被预先指定为补偿区域的矩阵存储器阵列，读出装置在某些信号线上根据解码信号指定的区域中的存储器单元输出数据;检测器，用于检测所述地址与所述一些信号线上的解码信号中的所述补偿区域相关，所述补偿区域是预处理的，与一些信号线相关联的固定数据输出电路，以及用于根据检测信号将预定数据合并到从存储器单元读出的数据的预定部分中以输出合并数据的固定数据输出电路。固定数据输出电路由控制电路根据合并控制信号进行控制，以输出从存储单元读出的数据，而不进行合并操作。

6. 发明申请

US20060174052A1 Integrated circuit and information processing device 审中-公开
标题翻译：集成电路和信息处理装置
公开(公告)号：US20060174052A1
公开(公告)日：2006-08-03
申请号：US11047670
申请日：2005-02-02
申请人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
发明人： Nobukazu Kondo , Kei Suzuki , Kouki Noguchi , Itaru Nonomura
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： In an LSI system using an on-chip bus, when a transfer on the bus is delayed due to a fully loaded buffer in a destination module, a source module cannot proceed to the next processing. Such an unwanted situation is eliminated by a transferring buffer which is provided on a transfer path in an on-chip bus on the LSI for temporarily storing transfer data. With this transferring buffer, even if a buffer within a slave module, specified as the destination, is fully loaded and cannot accept any more transfer, a bus master can transfer data to the transferring buffer provided on the on-chip bus. Thus, the bus master is not kept waiting for execution of a transfer, irrespective of the state of the buffer within the slave, thereby improving the processing performance of the entire system.
摘要翻译：在使用片上总线的LSI系统中，当总线上的传输由于目的地模块中的满载缓冲器而被延迟时，源模块不能进行下一个处理。通过在LSI上的片上总线的传送路径上提供的用于临时存储传送数据的传送缓冲器来消除这种不希望的情况。使用此传输缓冲区，即使指定为目标的从模块中的缓冲区已完全加载，也不能接受任何更多传输，总线主机可将数据传输到片上总线上提供的传输缓冲区。因此，无论总线主机中的缓冲器的状态如何，总线主机不会等待执行转移，从而提高整个系统的处理性能。

7. 发明授权

US06343357B1 Microcomputer and dividing circuit 失效
标题翻译：微电脑和分频电路
公开(公告)号：US06343357B1
公开(公告)日：2002-01-29
申请号：US09632332
申请日：2000-08-03
申请人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
发明人： Shumpei Kawasaki , Eiji Sakakibara , Kaoru Fukada , Takanaga Yamazaki , Yasushi Akao , Shiro Baba , Toshimasa Kihara , Keiichi Kurakazu , Takashi Tsukamoto , Shigeki Masumura , Yasuhiro Tawara , Yugo Kashiwagi , Shuya Fujita , Katsuhiko Ishida , Noriko Sawa , Yoichi Asano , Hideaki Chaki , Tadahiko Sugawara , Masahiro Kainaga , Kouki Noguchi , Mitsuru Watabe
IPC分类号： G06F1500
CPC分类号： G06F7/535 , G06F9/30 , G06F9/3001 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/30189 , G06F9/322 , G06F9/324 , G06F9/3557 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F2207/5352
摘要： A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.
摘要翻译：采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。并且，通过注意代码位来执行编码除法的控制。

8. 发明授权

US06279063B1 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller 有权
标题翻译：具有至少第一和第二微型计算机的微机系统，每个微型计算机均可在主模式和从属模式下操作，具有可配置的总线访问控制终端和总线使用优先级控制器
公开(公告)号：US06279063B1
公开(公告)日：2001-08-21
申请号：US09467087
申请日：1999-12-10
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1300
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

9. 发明授权

US06223265B1 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal 有权
标题翻译：单片机同步控制外部同步存储器，响应存储器时钟信号和时钟使能信号
公开(公告)号：US06223265B1
公开(公告)日：2001-04-24
申请号：US09192093
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1200
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

10. 发明授权

US06212620B1 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals 有权
标题翻译：单片机可在主从模式下工作，并具有可配置的总线控制端子
公开(公告)号：US06212620B1
公开(公告)日：2001-04-03
申请号：US09191313
申请日：1998-11-13
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F1500
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

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