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1. 发明申请

US20100155942A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100155942A1
公开(公告)日：2010-06-24
申请号：US12713799
申请日：2010-02-26
申请人： Kouji TAKEMURA , Noriyuki Nagai , Takatoshi Osumi
发明人： Kouji TAKEMURA , Noriyuki Nagai , Takatoshi Osumi
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L24/12 , H01L24/05 , H01L24/06 , H01L2224/0401 , H01L2224/13099 , H01L2224/16 , H01L2224/16225 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15184
摘要： A semiconductor device includes: a connection electrode formed on a side of a semiconductor element substrate opposed to a bump, where the semiconductor element substrate includes a semiconductor element; a passivation layer covering the semiconductor element substrate and an end portion of the connection electrode; and a barrier metal layer covering the connection electrode and a portion of the passivation layer so as to be electrically connected to the bump. A recess is formed in a portion of the passivation layer connected with the barrier metal layer.
摘要翻译：半导体器件包括：形成在半导体元件衬底的与凸块相对的一侧的连接电极，其中半导体元件衬底包括半导体元件; 覆盖半导体元件基板的钝化层和连接电极的端部; 以及阻挡金属层，其覆盖所述连接电极和所述钝化层的一部分，以便电连接到所述凸块。在与阻挡金属层连接的钝化层的一部分中形成凹部。

2. 发明授权

US08067950B2 Semiconductor device including chip 有权
标题翻译：半导体器件包括芯片
公开(公告)号：US08067950B2
公开(公告)日：2011-11-29
申请号：US12711829
申请日：2010-02-24
申请人： Noriyuki Nagai , Takatoshi Osumi
发明人： Noriyuki Nagai , Takatoshi Osumi
IPC分类号： G01R31/3187 , G01R31/02
CPC分类号： H01L21/563 , G01R31/2884 , H01L22/32 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/0401 , H01L2224/05012 , H01L2224/05014 , H01L2224/05022 , H01L2224/05124 , H01L2224/05572 , H01L2224/05655 , H01L2224/0603 , H01L2224/06051 , H01L2224/06135 , H01L2224/06155 , H01L2224/06177 , H01L2224/06179 , H01L2224/06515 , H01L2224/131 , H01L2224/13144 , H01L2224/1403 , H01L2224/14135 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/351 , H01L2924/00014 , H01L2924/01014 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.
摘要翻译：其中芯片10安装在板上的半导体器件包括：设置在芯片10上并电连接到芯片10中的内部电路的焊盘组A. 以及设置在除了设置有焊盘组A的芯片10的区域之外的芯片10的区域上的测试焊盘图案B. 焊盘组A包括：形成在芯片10的主表面上的焊盘12a; 分别形成在焊盘12a上的阻挡金属层之间的突起16a，并且电连接到电路板。测试垫图案B包括：形成在芯片10的主表面上的测试焊盘12b; 分别形成在测试焊盘12b上的测试凸块16b和介于其间的测试阻挡金属层，以及电连接相邻的测试焊盘12b的互连11b。

3. 发明授权

US08212366B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08212366B2
公开(公告)日：2012-07-03
申请号：US12913308
申请日：2010-10-27
申请人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L21/56
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
摘要翻译：形成输入/输出单元以便在半导体芯片的表面上与角单元相邻地周边布置，并且在相应的输入/输出单元上形成电极焊盘。电极焊盘被配置成Z字形排列，以形成内部和外部焊盘阵列。然而，在形成内焊盘阵列的电极焊盘中，与角电池两侧相邻的预定区域中的那些电极焊盘没有布置，使得凸起接合到半导体芯片的载体的互连图案和通孔被阻止变得复杂。

4. 发明申请

US20070138638A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070138638A1
公开(公告)日：2007-06-21
申请号：US11594875
申请日：2006-11-09
申请人： Yukitoshi Ota , Noriyuki Nagai , Tsuyoshi Hamatani
发明人： Yukitoshi Ota , Noriyuki Nagai , Tsuyoshi Hamatani
IPC分类号： H01L23/52
CPC分类号： H01L23/522 , H01L22/32 , H01L24/05 , H01L2224/02166 , H01L2224/05001 , H01L2224/05093 , H01L2224/0554 , H01L2224/05554 , H01L2224/45124 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01082 , H01L2924/04953 , H01L2924/05042 , H01L2924/00 , H01L2224/48
摘要： In a semiconductor device having a multilayer interconnection structure, wires are formed by a damascene process, at least part of electrode pads includes a first conductive layer having a region provided for an electrical connection with an external unit. Herein, the first conductive layer is formed on a passivation film that is formed a semiconductor substrate and is indispensable for the multilayer interconnection structure.
摘要翻译：在具有多层互连结构的半导体器件中，通过镶嵌工艺形成导线，至少部分电极焊盘包括具有设置用于与外部单元的电连接的区域的第一导电层。这里，第一导电层形成在形成半导体衬底的钝化膜上，对于多层互连结构是不可或缺的。

5. 发明申请

US20060175714A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060175714A1
公开(公告)日：2006-08-10
申请号：US11374057
申请日：2006-03-14
申请人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
摘要翻译：形成输入/输出单元以便在半导体芯片的表面上与角单元相邻地周边布置，并且在相应的输入/输出单元上形成电极焊盘。电极焊盘被配置成Z字形排列，以形成内部和外部焊盘阵列。然而，在形成内焊盘阵列的电极焊盘中，与角电池两侧相邻的预定区域中的那些电极焊盘没有布置，使得凸起接合到半导体芯片的载体的互连图案和通孔被阻止变得复杂。

6. 发明授权

US06856022B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06856022B2
公开(公告)日：2005-02-15
申请号：US10402240
申请日：2003-03-31
申请人： Naoki Nojiri , Koji Takemura , Noriyuki Nagai , Atsushi Doi
发明人： Naoki Nojiri , Koji Takemura , Noriyuki Nagai , Atsushi Doi
IPC分类号： H01L23/485 , H01L23/528 , H01L23/58 , H01L27/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L22/32 , H01L23/5286 , H01L24/49 , H01L27/0207 , H01L27/0251 , H01L2224/05093 , H01L2224/05552 , H01L2224/05554 , H01L2224/06153 , H01L2224/4943 , H01L2924/00014 , H01L2924/01005 , H01L2924/01015 , H01L2924/01033 , H01L2924/13091 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.
摘要翻译：根据本发明，在位于半导体芯片周围的输入/输出电路部分中，电极焊盘被布置在一行中布置的多个输入/输出单元中的每一个之上。电极焊盘的宽度大于输入/输出单元的宽度，因此电极焊盘不能排列成一行，而是以两行错开排列。一行的电极焊盘被移位，使得它们不与输入/输出单元的内部端子重叠，而是设置在这些内部端子附近。电极焊盘之间的间隔被设定为至少由设计的隔离规则确定的设定距离的距离。

7. 发明授权

US07944059B2 Semiconductor device having a probing region 有权
标题翻译：具有探测区域的半导体器件
公开(公告)号：US07944059B2
公开(公告)日：2011-05-17
申请号：US11494705
申请日：2006-07-28
申请人： Noriyuki Nagai , Toshihiko Sakashita
发明人： Noriyuki Nagai , Toshihiko Sakashita
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L23/3114 , H01L24/12 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/45147 , H01L2224/48463 , H01L2224/48847 , H01L2924/014 , H01L2924/3025 , H01L2924/00014 , H01L2224/48824 , H01L2924/00
摘要： In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.
摘要翻译：在半导体装置中，垫金属具有位于探针区域正下方的至少一部分，并且该部分被分割成与探针的行进方向平行设置的多个窄金属层。因此，可以提高焊盘金属的表面平坦度，并且防止半导体器件的特性劣化而没有处理中的复杂性和芯片尺寸的增加。

8. 发明授权

US07675184B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07675184B2
公开(公告)日：2010-03-09
申请号：US12213410
申请日：2008-06-19
申请人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
发明人： Manabu Ohnishi , Koji Takemura , Noriyuki Nagai , Hoyeun Huh , Tomoyuki Nakayama , Atsushi Doi
IPC分类号： H01L23/28
CPC分类号： H01L24/06 , H01L23/3114 , H01L23/50 , H01L2224/0401 , H01L2224/05552 , H01L2224/05555 , H01L2224/06153 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/3011 , H01L2924/00012
摘要： Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.
摘要翻译：形成输入/输出单元以便在半导体芯片的表面上与角单元相邻地周边布置，并且在相应的输入/输出单元上形成电极焊盘。电极焊盘被配置成Z字形排列，以形成内部和外部焊盘阵列。然而，在形成内焊盘阵列的电极焊盘中，与角电池两侧相邻的预定区域中的那些电极焊盘没有布置，使得凸起接合到半导体芯片的载体的互连图案和通孔被阻止变得复杂。

9. 发明授权

US07341349B2 Ophthalmologic apparatus and ophthalmologic chart 有权
标题翻译：眼科仪器和眼科图
公开(公告)号：US07341349B2
公开(公告)日：2008-03-11
申请号：US10495467
申请日：2002-11-15
申请人： Yasufumi Fukuma , Kohji Nishio , Takefumi Hayashi , Eiichi Yanagi , Noriyuki Nagai , Yasuo Kato , Yukio Ikezawa , Mineki Hayafuji , Tadashi Okamoto , Masakazu Hayashi
发明人： Yasufumi Fukuma , Kohji Nishio , Takefumi Hayashi , Eiichi Yanagi , Noriyuki Nagai , Yasuo Kato , Yukio Ikezawa , Mineki Hayafuji , Tadashi Okamoto , Masakazu Hayashi
IPC分类号： A61B3/02
CPC分类号： A61B3/08 , A61B3/032 , A61B3/152
摘要： An optometric apparatus 2 according to the present invention comprises a body portion 5r provided with an optical system for a right eye for projecting a chart for the right eye in order to inspect visual function of both eye of an examinee and a body portion 5l provided with an optical system for a left eye for projecting a chart for the left eye, the optical systems for the right and left eyes projecting the same fusion patterns to perform fusion of the both eyes of the examinee.
摘要翻译：根据本发明的验光装置2包括主体部分5r，其设置有用于右眼的光学系统用于投射右眼的图表，以便检查受检者的双眼的视觉功能和身体部分5l 设置有用于左眼投射左眼的光学系统，用于左眼和左眼的光学系统投射相同的融合图案以执行受检者的双眼的融合。

10. 发明授权

US07170620B2 Print job management apparatus 有权
标题翻译：打印作业管理装置
公开(公告)号：US07170620B2
公开(公告)日：2007-01-30
申请号：US09988037
申请日：2001-11-16
申请人： Kazuhito Gassho , Noriyuki Nagai
发明人： Kazuhito Gassho , Noriyuki Nagai
IPC分类号： G06K1/00 , G06F3/12 , G06F13/14 , G06F19/00 , B41B27/40
CPC分类号： G06F3/1286 , G06F3/1208 , G06F3/1267 , Y10S707/99937
摘要： The technique of the present invention facilitates execution of proof printing, prior to main printing. In a printing system constructed via a network LAN, a printer PRT includes a job management apparatus that manages statuses of print jobs in conformity with International Standard ISO/IEC10175-1. The job management apparatus has a proofComplete control module 6 in addition to diverse functional blocks for processing the print jobs based on the International Standard. The proofComplete control module 6 functions to hold a print job with attribute information representing proof printing after conclusion of proof printing. Separate management of the print job with the proof printing attribute enables a single print job to be utilized for both proof printing and main printing. This arrangement effectively enhances the utility.
摘要翻译：本发明的技术有利于在主打印之前执行证明印刷。在通过网络LAN构建的打印系统中，打印机PRT包括管理符合国际标准ISO / IEC10175-1的打印作业状态的作业管理装置。除了用于处理基于国际标准的打印作业的各种功能块之外，作业管理装置还具有校验完全控制模块6。 proofComplete控制模块6用于在证明打印结束之后保存具有表示证明打印的属性信息的打印作业。使用校样打印属性对打印作业的单独管理使得能够将单个打印作业用于证明打印和主打印。这种安排有效地提高了效用。

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