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    • 1. 发明申请
    • DELAY ADJUSTMENT DEVICE AND DELAY ADJUSTMENT METHOD
    • 延迟调整设备和延迟调整方法
    • US20110128060A1
    • 2011-06-02
    • US13056020
    • 2010-05-27
    • Kouichi IshinoTakeshi NakayamaMasahiro Ishii
    • Kouichi IshinoTakeshi NakayamaMasahiro Ishii
    • H03H11/26
    • G06F13/1689
    • Provided is a delay adjustment device for adjusting delay of a strobe signal, which specifies when to read a data signal on a data line, with respect to the data signal in order to perform data transfer with an external memory. A testing unit 150 included in a delay adjustment unit is provided with a memory bandwidth monitoring unit 212 that monitors memory bandwidth in use on the data line used for data transfer with a memory circuit. The testing unit 150 performs delay adjustment when the memory bandwidth in use is lower than a predetermined threshold. Delay adjustment is performed by delaying the strobe signal from the data signal by a variety of predetermined delays and determining whether data transfer is successful at each delay, calculating an optimal delay, and thereafter delaying the strobe signal by the calculated delay.
    • 提供了一种用于调整选通信号的延迟的延迟调整装置,该选通信号指定何时读取数据线上的数据信号,以便与外部存储器进行数据传送。 包括在延迟调整单元中的测试单元150设置有存储带宽监视单元212,其利用用于与存储器电路进行数据传输的数据线一起使用中的存储器带宽。 当使用的存储器带宽低于预定阈值时,测试单元150执行延迟调整。 通过将数据信号的选通信号延迟各种预定的延迟并确定数据传输是否在每个延迟成功,计算最佳延迟,然后将选通信号延迟所计算的延迟来执行延迟调整。
    • 2. 发明授权
    • Delay adjustment device and delay adjustment method
    • 延时调整装置和延时调整方法
    • US08363492B2
    • 2013-01-29
    • US13056020
    • 2010-05-27
    • Kouichi IshinoTakeshi NakayamaMasahiro Ishii
    • Kouichi IshinoTakeshi NakayamaMasahiro Ishii
    • G11C7/00
    • G06F13/1689
    • Provided is a delay adjustment device for adjusting delay of a strobe signal, which specifies when to read a data signal on a data line, with respect to the data signal in order to perform data transfer with an external memory. A testing unit 150 included in a delay adjustment unit is provided with a memory bandwidth monitoring unit 212 that monitors memory bandwidth in use on the data line used for data transfer with a memory circuit. The testing unit 150 performs delay adjustment when the memory bandwidth in use is lower than a predetermined threshold. Delay adjustment is performed by delaying the strobe signal from the data signal by a variety of predetermined delays and determining whether data transfer is successful at each delay, calculating an optimal delay, and thereafter delaying the strobe signal by the calculated delay.
    • 提供了一种用于调整选通信号的延迟的延迟调整装置,该选通信号指定何时读取数据线上的数据信号,以便与外部存储器进行数据传送。 包括在延迟调整单元中的测试单元150设置有存储带宽监视单元212,其利用用于与存储器电路进行数据传输的数据线一起使用中的存储器带宽。 当使用的存储器带宽低于预定阈值时,测试单元150执行延迟调整。 通过将数据信号的选通信号延迟各种预定的延迟并确定数据传输是否在每个延迟成功,计算最佳延迟,然后将选通信号延迟所计算的延迟来执行延迟调整。
    • 8. 发明申请
    • DATA TRANSFER CONTROL DEVICE, DATA TRANSFER DEVICE, DATA TRANSFER CONTROL METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT USING RECONFIGURED CIRCUIT
    • 数据传输控制设备,数据传输设备,数据传输控制方法和使用重新配置的电路的半导体集成电路
    • US20100042751A1
    • 2010-02-18
    • US12522490
    • 2008-10-24
    • Kouichi IshinoTakashi MorimotoKoji Asai
    • Kouichi IshinoTakashi MorimotoKoji Asai
    • G06F3/00
    • G11C7/10G06F13/1694
    • A semiconductor integrated circuit ensures to reserve a required memory bandwidth at low cost. A memory bandwidth monitoring unit 1210 calculates a required memory bandwidth, monitors the usage condition of the memory, and outputs the following information to a reconfiguration control unit 1120. The information is necessary to reconfigure a reconfiguration unit 1110 into a logic unit and a temporary buffer both of which are scalable depending on the usage condition. According to information, the reconfiguration control unit 1120 controls the reconfiguration unit 1110. The buffer is for storing data accessed to or from the memory by each bus master. The logic unit acts as a bus master that only uses a portion of the memory bandwidth that remains unused during the time no access request to the data storage unit 1002 issued by a bus master unit having a higher priority level is being executed.
    • 半导体集成电路确保以低成本保留所需的存储器带宽。 存储器带宽监视单元1210计算所需的存储器带宽,监视存储器的使用状况,并将以下信息输出到重新配置控制单元1120.该信息对于将重新配置单元1110重新配置为逻辑单元和临时缓冲器 这两者都可以根据使用条件进行扩展。 根据信息,重新配置控制单元1120控制重新配置单元1110.缓冲器用于存储由每个总线主机访问或从存储器访问的数据。 逻辑单元充当总线主机,其仅在没有执行具有较高优先级的总线主机单元发出的对数据存储单元1002的访问请求的时间内仅使用保持未使用的存储器带宽的一部分。
    • 10. 发明授权
    • Bus communication apparatus that uses shared memory
    • 使用共享存储器的总线通信设备
    • US07774529B2
    • 2010-08-10
    • US12167153
    • 2008-07-02
    • Kouichi IshinoHideyuki KanzakiKazuhiro Watanabe
    • Kouichi IshinoHideyuki KanzakiKazuhiro Watanabe
    • G06F13/00G06F13/36G06F13/14G06F13/28
    • G06F13/1663
    • Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arbitration completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12. Based on the memory access completion notification signal, the communication origin master 101 issues a command issue permission signal to the communication destination master 102, and the communication destination master 102 generates and issues a command for accessing the shared memory 12.
    • 基于通信原点主机101选择性地使用仲裁完成通知信号和存储器访问完成通知信号,使用共享存储器的总线通信中的总线传输效率得到改善。 基于仲裁完成通知信号,通信原点主机101向通信目的地主机102发出命令发出许可信号,通信目的地主机102生成并发出用于访问共享存储器12的命令。基于存储器访问完成 通信源主机101向通信目的地主机102发出命令发出许可信号,并且通信目的地主机102产生并发出访问共享存储器12的命令。