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1. 发明授权

US08842475B2 Configuration memory 有权
标题翻译：配置内存
公开(公告)号：US08842475B2
公开(公告)日：2014-09-23
申请号：US13603666
申请日：2012-09-05
申请人： Kosuke Tatsumura , Masato Oda , Koichiro Zaitsu , Atsushi Kawasumi , Mari Matsumoto , Shinichi Yasuda
发明人： Kosuke Tatsumura , Masato Oda , Koichiro Zaitsu , Atsushi Kawasumi , Mari Matsumoto , Shinichi Yasuda
IPC分类号： G11C11/34
CPC分类号： G11C16/06 , G11C7/06 , G11C16/26
摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.
摘要翻译：根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路配置数据输出节点。

2. 发明授权

US08921920B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08921920B2
公开(公告)日：2014-12-30
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L29/792 , H01L21/28 , G11C11/22 , G11C11/412 , G11C14/00 , H01L29/51 , H01L27/11 , H01L27/115 , H01L27/118
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

3. 发明申请

US20120326224A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120326224A1
公开(公告)日：2012-12-27
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru KAWANAKA , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru KAWANAKA , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L27/088
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

4. 发明授权

US08508192B2 Battery pack capable of calculating relative remaining capacity 有权
标题翻译：能够计算相对剩余容量的电池组
公开(公告)号：US08508192B2
公开(公告)日：2013-08-13
申请号：US12961898
申请日：2010-12-07
申请人： Shinichi Matsuura , Atsushi Kawasumi
发明人： Shinichi Matsuura , Atsushi Kawasumi
IPC分类号： H02J7/00
CPC分类号： H02J7/0021 , G01R31/362 , G01R31/3658 , H01M10/0525 , H01M10/486
摘要： A remaining capacity calculating section is provided that acquires a discharged capacity of a rechargeable battery based on a discharging current and a discharging time of the rechargeable battery, and calculates a relative remaining capacity of the rechargeable battery based on the discharged capacity and the fully-charged capacity of the rechargeable battery. The remaining capacity calculating section employs the rating capacity of the rechargeable battery or a learned fully-charged capacity as the fully-charged capacity when a high capacity mode is selected, and employs a capacity obtained by multiplying the rating capacity or learned fully-charged capacity by a predetermined factor not more than 1 as the fully-charged capacity when a long life mode is selected.
摘要翻译：提供剩余容量计算部分，其基于可再充电电池的放电电流和放电时间获取可再充电电池的放电容量，并且基于放电容量和充满电的电量计算可再充电电池的相对剩余容量充电电池的容量。当选择高容量模式时，剩余容量计算部分采用可再充电电池的额定容量或学习完全充电容量作为完全充电容量，并且采用通过将额定容量或学习完全充电容量当选择长寿命模式时，预定因子不大于1作为完全充电容量。

5. 发明申请

US20120127811A1 TIMING GENERATION CIRCUIT, SEMICONDUCTOR STORAGE DEVICE AND TIMING GENERATION METHOD 有权
标题翻译：时序生成电路，半导体存储器件和时序生成方法
公开(公告)号：US20120127811A1
公开(公告)日：2012-05-24
申请号：US13053702
申请日：2011-03-22
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C7/00 , H03K3/00 , G11C7/06
CPC分类号： G11C7/08
摘要： According to an embodiment, a semiconductor storage device includes a memory cell array, a plurality of sense amplifiers and a timing generation circuit. The memory cell array includes a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a plurality of memory cells provided in intersection portions of the plurality of word lines and the plurality of bit lines. The plurality of sense amplifiers is configured to detect a signal level of the corresponding bit lines. The timing generation circuit includes a timing selection circuit configured to select a timing in a preset order from among timings in which each bit line signal in the plurality of bit lines changes. The timing generation circuit is configured to generate activation timing to activate the plurality of sense amplifiers based on the selected timing.
摘要翻译：根据实施例，半导体存储装置包括存储单元阵列，多个读出放大器和定时生成电路。存储单元阵列包括多个字线，与多个字线交叉的多个位线，以及设置在多个字线和多个位线的交叉部分中的多个存储单元。多个读出放大器被配置为检测相应位线的信号电平。定时产生电路包括定时选择电路，其被配置为从多位位线中的每个位线信号改变的定时中以预定顺序选择定时。定时产生电路被配置为基于所选定时产生激活定时以激活多个读出放大器。

6. 发明授权

US08148950B2 Charging method 失效
标题翻译：充电方式
公开(公告)号：US08148950B2
公开(公告)日：2012-04-03
申请号：US12314483
申请日：2008-12-11
申请人： Shinichi Matsuura , Atsushi Kawasumi
发明人： Shinichi Matsuura , Atsushi Kawasumi
IPC分类号： H02J7/04 , H02J7/16 , H02J7/00
CPC分类号： H02J7/0091
摘要： A charging method includes first and second charging steps to charge a lithium-ion battery. In the first charging step, a temperature rise gradient of the battery is detected. A battery temperature when the battery is charged to a first predetermined capacity is predicted based on the detected gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that results in a battery temperature that is lower than a predetermined temperature, to the first predetermined capacity. In the second charging step, a temperature rise gradient of the battery is detected. A battery temperature when the battery is charged to a second predetermined capacity is predicted based on the gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that results in a temperature of the battery that is lower than the predetermined temperature, to the second predetermined capacity.
摘要翻译：充电方法包括对锂离子电池充电的第一和第二充电步骤。在第一充电步骤中，检测电池的升温梯度。基于检测到的梯度来预测电池充电到第一预定容量时的电池温度。充电电流根据预测温度进行控制。将电池以导致电池温度低于预定温度的电流充电至第一预定容量。在第二充电步骤中，检测电池的升温梯度。基于该梯度来预测将电池充电到第二预定容量时的电池温度。充电电流根据预测温度进行控制。电池以导致电池的温度低于预定温度的电流被充电到第二预定容量。

7. 发明申请

US20110013468A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110013468A1
公开(公告)日：2011-01-20
申请号：US12728167
申请日：2010-03-19
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/227 , G11C11/413
摘要： A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects an output signal that rises up at the latest timing among output signals output from the plurality of replica circuits respectively and outputs a detection signal. A delay circuit delays the detection signal. The sense amplifier circuit is activated based on the delayed signal.
摘要翻译：存储单元设置在字线和位线的交叉点。读出放大器电路感测并放大位线上的信号。复制电路包括被配置为固定地保留某些数据的复制单元。信号检测电路分别检测从多个复制电路输出的输出信号中的最新定时上升的输出信号，并输出检测信号。延迟电路延迟检测信号。基于延迟信号激活读出放大器电路。

8. 发明授权

US07746685B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07746685B2
公开(公告)日：2010-06-29
申请号：US12207949
申请日：2008-09-10
申请人： Atsushi Kawasumi , Takahiko Sasaki
发明人： Atsushi Kawasumi , Takahiko Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： SRAM cells are arranged in matrix along a first and a second bit line and a word line for single-ended reading of data from the second bit line. A first NMOS transistor and a first transfer transistor contained in the SRAM cell are formed in a first well with respective identical gate lengths and gate widths. A second NMOS transistor and a second transfer transistor contained in the SRAM cell are formed in a second well with respective identical gate lengths and gate widths. These gate widths are made wider than the gate widths of the first NMOS transistor and the first transfer transistor.
摘要翻译： SRAM单元沿着第一和第二位线和用于单端读取第二位线的数据的字线被排列成矩阵。包含在SRAM单元中的第一NMOS晶体管和第一传输晶体管形成在具有各自相同的栅极长度和栅极宽度的第一阱中。包含在SRAM单元中的第二NMOS晶体管和第二传输晶体管形成在具有各自相同的栅极长度和栅极宽度的第二阱中。这些栅极宽度比第一NMOS晶体管和第一转移晶体管的栅极宽度宽。

9. 发明授权

US07675804B2 Semiconductor integrated circuit device and semiconductor device including plurality of semiconductor circuits 失效
标题翻译：半导体集成电路器件和包括多个半导体电路的半导体器件
公开(公告)号：US07675804B2
公开(公告)日：2010-03-09
申请号：US11975470
申请日：2007-10-19
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C5/14
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit device includes a first semiconductor circuit, a second semiconductor circuit, a first control circuit and a second control circuit. The first and second semiconductor circuits are formed on a semiconductor substrate and operate using a voltage provided by an external power supply circuit as a power supply voltage. The first control circuit is formed on the semiconductor substrate and holds control information used to control the voltage generated by the external power supply circuit in accordance with operating performance of the first and second semiconductor circuits. The second control circuit controls a property of the first semiconductor circuit in accordance with the control information held by the first control circuit.
摘要翻译：半导体集成电路器件包括第一半导体电路，第二半导体电路，第一控制电路和第二控制电路。第一和第二半导体电路形成在半导体衬底上，并且使用由外部电源电路提供的电压作为电源电压进行操作。第一控制电路形成在半导体衬底上，并且保持用于根据第一和第二半导体电路的操作性能来控制由外部电源电路产生的电压的控制信息。第二控制电路根据由第一控制电路保持的控制信息控制第一半导体电路的特性。

10. 发明授权

US07535752B2 Semiconductor static random access memory device 失效
标题翻译：半导体静态随机存取存储器件
公开(公告)号：US07535752B2
公开(公告)日：2009-05-19
申请号：US11712254
申请日：2007-02-28
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/1104 , H01L27/1207
摘要： According to an aspect of the invention there is provided a semiconductor memory device, including a first inverter being composed of a first P-channel MOS transistor, a first N-channel MOS transistor, a second inverter being composed of a second p-channel MOS transistor and a second N-channel transistor, a data-retaining portion having a third N-channel MOS transistor, a fourth N-channel MOS transistor, a fifth N-channel MOS transistor and a sixth N-channel MOS transistor, a data-reading portion for reading out data stored in the data-retaining portion via a first bit line, including at least one N-channel MOS transistor, wherein gate widths of the fifth N-channel MOS transistor and the sixth N-channel MOS transistor, respectively, is larger than gate widths of the first N-channel MOS transistor, the second N-channel MOS transistor, the third N-channel MOS transistor, the fourth N-channel MOS transistor, the first P-channel MOS transistor and the second P-channel MOS transistor, respectively.
摘要翻译：根据本发明的一个方面，提供了一种半导体存储器件，包括第一反相器，其由第一P沟道MOS晶体管，第一N沟道MOS晶体管，第二反相器组成，第二反相器由第二P沟道MOS晶体管晶体管和第二N沟道晶体管，具有第三N沟道MOS晶体管，第四N沟道MOS晶体管，第五N沟道MOS晶体管和第六N沟道MOS晶体管的数据保持部，读取部分，用于经由包括至少一个N沟道MOS晶体管的第一位线读出存储在数据保持部分中的数据，其中第五N沟道MOS晶体管和第六N沟道MOS晶体管的栅极宽度分别为大于第一N沟道MOS晶体管，第二N沟道MOS晶体管，第三N沟道MOS晶体管，第四N沟道MOS晶体管，第一P沟道MOS晶体管和第二P栅极的栅极宽度通道MOS晶体管真诚地

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