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1. 发明授权

US08921920B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08921920B2
公开(公告)日：2014-12-30
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru Kawanaka , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L29/792 , H01L21/28 , G11C11/22 , G11C11/412 , G11C14/00 , H01L29/51 , H01L27/11 , H01L27/115 , H01L27/118
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

2. 发明申请

US20120326224A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120326224A1
公开(公告)日：2012-12-27
申请号：US13418620
申请日：2012-03-13
申请人： Shigeru KAWANAKA , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
发明人： Shigeru KAWANAKA , Kosuke Tatsumura , Naoki Yasuda , Jun Fujiki , Atsushi Kawasumi
IPC分类号： H01L27/088
CPC分类号： H01L21/28282 , G11C11/22 , G11C11/412 , G11C14/0081 , H01L27/1104 , H01L27/1156 , H01L27/11568 , H01L27/11807 , H01L29/518 , H01L29/792
摘要： A semiconductor device has a semiconductor substrate, and a semiconductor element having an FET on the semiconductor substrate and comprises a different threshold voltage depending on an OFF state and an ON state. The semiconductor element has an insulating film disposed above a part where a channel of the semiconductor substrate is formed, a gate electrode disposed above the insulating film, and a charge trap film disposed between the insulating film and the gate electrode, and to exchange more electrons with the gate electrode than with the channel.
摘要翻译：半导体器件具有半导体衬底和半导体衬底上具有FET的半导体元件，并且包括根据OFF状态和ON状态的不同阈值电压。半导体元件具有设置在形成半导体基板的沟道的部分上方的绝缘膜，设置在绝缘膜上方的栅电极和设置在绝缘膜和栅电极之间的电荷陷阱膜，并且交换更多的电子栅电极与通道相比。

3. 发明授权

US08058681B2 Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element 有权
标题翻译：非易失性半导体存储元件，非易失性半导体存储器以及用于操作非易失性半导体存储元件
公开(公告)号：US08058681B2
公开(公告)日：2011-11-15
申请号：US12405626
申请日：2009-03-17
申请人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： H01L29/792
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

4. 发明授权

US07943981B2 Semiconductor memory element 有权
标题翻译：半导体存储元件
公开(公告)号：US07943981B2
公开(公告)日：2011-05-17
申请号：US12233073
申请日：2008-09-18
申请人： Tsunehiro Ino , Naoki Yasuda , Koichi Muraoka , Jun Fujiki , Shoko Kikuchi , Keiko Ariyoshi
发明人： Tsunehiro Ino , Naoki Yasuda , Koichi Muraoka , Jun Fujiki , Shoko Kikuchi , Keiko Ariyoshi
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L29/42348 , H01L29/513 , H01L29/518
摘要： A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film.
摘要翻译：半导体存储元件包括：形成在半导体衬底上的隧道绝缘膜; 在隧道绝缘膜上形成具有Bevan簇的HfON电荷存储膜; 形成在HfON电荷存储膜上的阻挡膜; 以及形成在阻挡膜上的栅电极。

5. 发明申请

US20120205735A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120205735A1
公开(公告)日：2012-08-16
申请号：US13404073
申请日：2012-02-24
申请人： Naoki YASUDA , Jun Fujiki
发明人： Naoki YASUDA , Jun Fujiki
IPC分类号： H01L27/115
CPC分类号： H01L21/28282 , H01L27/1157 , H01L29/66833 , H01L29/792
摘要： In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.
摘要翻译：在一个实施例中，提供了一种非易失性半导体存储装置。该装置包括：多个非易失性存储单元。每个非易失性存储单元包括：第一半导体层，包括第一源极区，第一漏极区和第一沟道区; 形成在所述第一沟道区上的块绝缘膜; 形成在所述块绝缘膜上的电荷存储层; 形成在电荷存储层上的隧道绝缘膜; 形成在所述隧道绝缘膜上并且包括第二源极区域，第二漏极区域和第二沟道区域的第二半导体层。第二沟道区形成在隧道绝缘膜上，使得隧道绝缘膜位于第二源区和第二漏区之间。第一沟道区的掺杂剂杂质浓度高于第二沟道区的掺杂剂杂质浓度。

6. 发明申请

US20100080062A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME 失效
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US20100080062A1
公开(公告)日：2010-04-01
申请号：US12411746
申请日：2009-03-26
申请人： Jun Fujiki , Koichi Muraoka , Naoki Yasuda
发明人： Jun Fujiki , Koichi Muraoka , Naoki Yasuda
IPC分类号： G11C16/04 , H01L29/792 , G11C5/14 , G11C11/34
CPC分类号： G11C16/26 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L27/11565 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate including a first channel, and a source region and a drain region provided on both sides of the first channel; a first insulating film provided on the first channel; a charge retention layer provided on the first insulating film; a second insulating film provided on the charge retention layer; and a semiconductor layer including a second channel provided on the second insulating film, and a source region and a drain region provided on both sides of the second channel.
摘要翻译：非易失性半导体存储器件包括：包括第一沟道的半导体衬底和设置在第一沟道两侧的源极区和漏极区; 设置在第一通道上的第一绝缘膜; 设置在所述第一绝缘膜上的电荷保持层; 设置在电荷保持层上的第二绝缘膜; 以及包括设置在第二绝缘膜上的第二通道的半导体层，以及设置在第二通道两侧的源极区域和漏极区域。

7. 发明申请

US20100078704A1 SEMICONDUCTOR STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储元件及其制造方法
公开(公告)号：US20100078704A1
公开(公告)日：2010-04-01
申请号：US12404648
申请日：2009-03-16
申请人： Tsunehiro Ino , Shosuke Fujii , Jun Fujiki , Akira Takashima , Masao Shingu , Daisuke Matsushita , Naoki Yasuda , Koichi Muraoka
发明人： Tsunehiro Ino , Shosuke Fujii , Jun Fujiki , Akira Takashima , Masao Shingu , Daisuke Matsushita , Naoki Yasuda , Koichi Muraoka
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L29/517 , H01L29/66833
摘要： A semiconductor storage element includes: a source region and a drain region provided in a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate between the source region and the drain region; a charge storage film provided on the tunnel insulating film; a block insulating film provided on the charge storage film; a gate electrode provided on the block insulating film; and a region containing a gas molecule, the region provided in a neighborhood of an interface between the charge storage film and the block insulating film.
摘要翻译：半导体存储元件包括：设置在半导体衬底中的源极区域和漏极区域; 设置在所述源极区域和所述漏极区域之间的所述半导体衬底上的隧道绝缘膜; 设置在所述隧道绝缘膜上的电荷存储膜; 设置在电荷存储膜上的块状绝缘膜; 设置在所述块绝缘膜上的栅电极; 以及包含气体分子的区域，所述区域设置在电荷存储膜和块绝缘膜之间的界面附近。

8. 发明授权

US08704290B2 Nonvolatile semiconductor memory element, nonvolatile semiconductor memory, and method for operating nonvolatile semiconductor memory element 有权
标题翻译：非易失性半导体存储元件，非易失性半导体存储器以及用于操作非易失性半导体存储元件的方法
公开(公告)号：US08704290B2
公开(公告)日：2014-04-22
申请号：US13619223
申请日：2012-09-14
申请人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Masao Shingu , Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： H01L29/66
CPC分类号： H01L29/7883 , G11C11/40 , G11C16/0408 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L27/11582 , H01L29/4234 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/788 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储元件，包括：半导体衬底，包括：源极区; 漏区; 和通道区域; 形成在沟道区上的下绝缘膜; 电荷存储膜，形成在下绝缘膜上并存储数据; 形成在电荷存储膜上的上绝缘膜; 以及形成在所述上绝缘膜上的控制栅极，其中所述上绝缘膜包括：第一绝缘膜; 以及与所述第一绝缘膜层压的第二绝缘膜，并且其中所述第一绝缘膜形成为具有比所述第二绝缘膜的陷阱级密度大的陷阱级密度。

9. 发明授权

US08569823B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569823B2
公开(公告)日：2013-10-29
申请号：US13235970
申请日：2011-09-19
申请人： Tsunehiro Ino , Masao Shingu , Shosuke Fujii , Akira Takashima , Daisuke Matsushita , Jun Fujiki , Naoki Yasuda , Yasushi Nakasaki , Koichi Muraoka
发明人： Tsunehiro Ino , Masao Shingu , Shosuke Fujii , Akira Takashima , Daisuke Matsushita , Jun Fujiki , Naoki Yasuda , Yasushi Nakasaki , Koichi Muraoka
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , H01L21/28282 , H01L27/11568 , H01L29/517 , H01L29/66833 , H01L29/792
摘要： According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.
摘要翻译：根据一个实施例，半导体器件包括半导体区域，设置在半导体区域上的隧道绝缘膜，设置在隧道绝缘膜上并具有包含立方体区域的氧化铪的电荷存储绝缘膜，设置在电荷存储绝缘膜和设置在块绝缘膜上的控制栅电极。

10. 发明授权

US08391075B2 Nonvolatile semiconductor memory device and method for driving same 有权
公开(公告)号：US08391075B2
公开(公告)日：2013-03-05
申请号：US13239964
申请日：2011-09-22
申请人： Jun Fujiki , Naoki Yasuda , Koichi Muraoka
发明人： Jun Fujiki , Naoki Yasuda , Koichi Muraoka
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , G11C16/3454 , G11C16/3459
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory string including a plurality of memory cells and, a driving unit. In sequentially reading data stored in the memory cells by applying a first signal to the memory cells, a second signal is applied to a second cell. The driving unit applies a third signal to the gate electrodes of all the memory cells prior to the sequential reading. The third signal has a voltage smaller than the second signal and time duration equal to or more than that of a sum of time duration during which the first signal is applied to all the memory cells. In a period prior to the third signal application, the driving unit performs at least one of applying a fourth signal to the gate electrodes and matching a potential of the gate electrodes with that of the semiconductor layer.

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