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1. 发明申请

WO2006134540A1 ELECTRONIC DEVICE, METHOD FOR FRAME SYNCHRONIZATION, AND MOBILE DEVICE. 审中-公开
标题翻译：电子设备，帧同步方法和移动设备。
公开(公告)号：WO2006134540A1
公开(公告)日：2006-12-21
申请号：PCT/IB2006/051860
申请日：2006-06-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RADULESCU, Andrei , VAN DEN HAMER, Peter
发明人： RADULESCU, Andrei , VAN DEN HAMER, Peter
IPC分类号： H04L12/64 , H04J3/06 , G06F1/04
CPC分类号： H04L12/2854 , H04J3/0647 , H04J3/0676 , H04L7/02 , H04L45/00 , H04L47/26 , H04L2007/045
摘要： An electronic device is provided with a plurality of iunctional units (1-10) for communicating at least primary and secondary data (ISOC; BE) based on frames (FR) each being divided into a number of time slot (SL), at least one network node (S1-S4) for coupling functional units (1-10) comprising at least one port (P1, P2, ..., Pk) having an associated receiver port unit (RX 1 , RX 2 , ..., RX k ) for receiving at least primary and secondary data (ISOC; BE) from one of the plurality of iunctional units (1-10) in one of at least one first clock domain; and an associated transmitter port unit (TX 1 , TX 2 , ..., TX k ) for transmitting at least primary and secondary data (ISOC; BE) to another one of the plurality of iunctional units (1-10) in one of at least one second clock domain. The at least one second clock domain is different from the at least one first clock domain. A time indication register (t[port]) is provided for storing information relating to the relative time position of a frame being received via the receiver port unit (RX 1 , RX 2 , ..., RX k ) associated to one of the at least one ports (P1 , P2, ... , Pk) and of a frame being transmitted via the transmitter port unit (TX 1 , TX 2 , ..., TX k ) associated to the one of the at least one ports (P1, P2, ..., Pk), wherein the time indication register (t[port]) is updated according to at least the primary and/or secondary data (ISO; BE) being received via the receiver port unit (RX 1 , RX 2 , ..., RX k ) associated to the one of the at least one ports (P1, P2, ..., Pk). A timer managing means (TMM) is provided for monitoring the at least primary and secondary data (ISOC; BE) received via the receiver port (RX 1 , RX 2 , ..., RX k ) associated to one of the at least one ports (P1, P2, ..., Pk) in one of the at least one first clock domain and for pausing the transmission of at least the primary data (ISOC) via the transmitter port unit (TX 1 , TX 2 , ..., TX k ) associated to the one of the at least one ports (P1, P2, ..., Pk), in one of the at least one second clock domain, if the value of the time indication register exceeds a predetermined threshold.
摘要翻译：电子设备具有多个功能单元（1-10），用于至少基于每个被划分为多个时隙（SL）的帧（FR）至少传送主数据和次数据（ISOC; BE），至少用于耦合功能单元（1-10）的一个网络节点（S1-S4），其包括具有相关联的接收器端口单元（RX＆lt; 1＆gt; 1）的至少一个端口（P1，P2，...，Pk）用于从所述多个功能单元（1-10）中的一个接收至少主要和次要数据（ISOC; BE）的接收机（RX 2，...，在至少一个第一时钟域中的一个中; 以及用于发送至少主要和次要数据的相关联的发射机端口单元（TX 1，TX 2，...，TX＆lt; k＆gt;）， ISOC; BE）到至少一个第二时钟域之一中的多个功能单元（1-10）中的另一个。至少一个第二时钟域与至少一个第一时钟域不同。提供时间指示寄存器（t [端口]），用于存储与通过接收器端口单元接收的帧的相对时间位置相关的信息（RX <1> 2 1，TX <2>，...，TX < ，P k），其中所述时间指示寄存器（t [端口]）根据至少经由所述接收器端口单元（RX＆lt; 1＆gt; 1）接收的主数据和/或次要数据（ISO; BE）与所述至少一个端口（P1，P2，...，Pk）中的所述一个端口相关联的，与所述至少一个端口（P1，P2，...，Pk）中的所述一个端口相关联的RX 2，... RX RX。提供了定时器管理装置（TMM），用于监视经由接收器端口（RX 1，RX 2）接收的至少主要和次要数据（ISOC; BE）。与所述至少一个第一时钟域之一中的至少一个端口（P1，P2，...，Pk）中的一个端口相关联并且用于暂停所述至少一个第一时钟域经由发送器端口单元（TX＆lt; 1＆gt;，TX＆lt; 2＆gt;，...，TX＆lt; k＆gt;）的主数据（ISOC）至少与如果时间指示寄存器的值超过预定阈值，则在至少一个第二时钟域之一中的至少一个端口（P1，P2，...，Pk）中的一个。

2. 发明申请

WO2002095672A1 SELF-DESCRIPTIVE DATA TAG 审中-公开
标题翻译：自我描述数据标签
公开(公告)号：WO2002095672A1
公开(公告)日：2002-11-28
申请号：PCT/IB2002/001704
申请日：2002-05-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： VAN DEN HAMER, Peter , HOLLMANN, Hendrik, D., L. , BODLAENDER, Maarten, P.
IPC分类号： G06K19/07
CPC分类号： G06K19/07 , G06F17/218 , G06F17/2258 , G06F17/271 , G06F17/3028
摘要： A data tag containing self-descriptive data, a method for reading such a data tag and a system for interpreting such a data tag are disclosed. Characterizing information about a first data element (112) stored in a memory (310) of the data tag (300) is stored in a first header (110) preceding a first data element (112). In addition, characterizing information about a second data element (116) stored in the memory (310) of the data tag (300) is stored in a second header (114) preceding a second data element (318). The application of a multitude of descriptive headers, each characterizing a data element stored in the data tag memory (310), facilitates flexible data storage on such devices. Furthermore, it also facilitates data compression due to the fact that field lengths can be characterized as well, thus excluding the presence of redundant bits in the data stored in the memory (310).
摘要翻译：公开了一种包含自描述数据的数据标签，用于读取这种数据标签的方法和用于解释这样的数据标签的系统。存储在数据标签（300）的存储器（310）中的关于第一数据元素（112）的信息被存储在第一数据元素（112）之前的第一报头（110）中。此外，存储在数据标签（300）的存储器（310）中的关于第二数据元素（116）的信息的特征存储在第二数据元素（318）之前的第二标题（114）中。多个描述性头部的应用，每个表征存储在数据标签存储器（310）中的数据元素，有助于这种设备上的灵活数据存储。此外，由于也可以对场长进行表征，从而排除存储在存储器（310）中的数据中的冗余位的存在，因此也有利于数据压缩。

3. 发明申请

WO2006131900A3 MEMORY CONTROLLER AND METHOD FOR COUPLING A NETWORK AND A MEMORY 审中-公开
公开(公告)号：WO2006131900A3
公开(公告)日：2006-12-14
申请号：PCT/IB2006/051842
申请日：2006-06-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , VAN DEN HAMER, Peter , CHAUHAN, Atul, P., S.
发明人： BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , VAN DEN HAMER, Peter , CHAUHAN, Atul, P., S.
IPC分类号： G06F13/16
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).

4. 发明申请

WO2006059283A3 STREAMING MEMORY CONTROLLER 审中-公开
公开(公告)号：WO2006059283A3
公开(公告)日：2006-06-08
申请号：PCT/IB2005/053970
申请日：2005-11-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
发明人： BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
IPC分类号： H04L12/56
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).

5. 发明申请

WO2006092764A1 SYSTEM AND METHOD FOR SYNCHRONISING A DATA PROCESSING NETWORK 审中-公开
标题翻译：用于同步数据处理网络的系统和方法
公开(公告)号：WO2006092764A1
公开(公告)日：2006-09-08
申请号：PCT/IB2006/050632
申请日：2006-03-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HEKSTRA-NOWACKA, Ewa , VAN DEN HAMER, Peter , VAN BERKEL, Cornelis, H. , RADULESCU, Andrei
发明人： HEKSTRA-NOWACKA, Ewa , VAN DEN HAMER, Peter , VAN BERKEL, Cornelis, H. , RADULESCU, Andrei
IPC分类号： H04J3/06
CPC分类号： H04J3/0635 , H04L7/0008
摘要： A data processing system according to the invention comprising a group of at least a first and a second module, wherein each module has a data processing facility, a clock for timing data transmissions from the module to another module, a time-slot counter for counting a number of time slots which are available for transmission of data. The modules have a first operational state wherein the counted number of time slots is less than or equal to a predetermined number, in which operational state data transmission is enabled, and a second operational state wherein the number is in excess of the predetermined number, in which second operational state data transmission is disabled, Each module has a notifying facility for notifying when it is in the second operational state. The data processing system has at least one detecting facility that detects whether the other modules have notified that they are in the second operational state and the modules each have an initialization facility for resetting the time-slot counter when the module is in the second operational state and each of the other modules has notified that it is in the second operational state.
摘要翻译：根据本发明的数据处理系统包括至少第一和第二模块的组，其中每个模块具有数据处理设施，用于从模块到另一模块的定时数据传输的时钟，用于计数的时隙计数器可用于传输数据的多个时隙。模块具有第一操作状态，其中计数的时隙数小于或等于预定数量，其中操作状态数据传输被启用，以及第二操作状态，其中数量超过预定数量，在哪个第二操作状态数据传输被禁用，每个模块都有一个通知设备，用于通知何时处于第二个操作状态。数据处理系统具有至少一个检测装置，其检测其他模块是否已经通知它们处于第二操作状态，并且模块各自具有用于当模块处于第二操作状态时复位时隙计数器的初始化设施并且每个其他模块已经通知它处于第二操作状态。

6. 发明授权

EP1820309B1 STREAMING MEMORY CONTROLLER 有权
标题翻译： STREAMING存储器控制
公开(公告)号：EP1820309B1
公开(公告)日：2008-08-27
申请号：EP05850071.1
申请日：2005-11-30
申请人： Koninklijke Philips Electronics N.V.
发明人： BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
IPC分类号： H04L12/56
CPC分类号： H04L49/9063 , G06F13/1673 , H04L49/90
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).

7. 发明公开

EP1397777A1 SELF-DESCRIPTIVE DATA TAG 有权
标题翻译：自描述性MEDIA
公开(公告)号：EP1397777A1
公开(公告)日：2004-03-17
申请号：EP02771686.9
申请日：2002-05-16
申请人： Koninklijke Philips Electronics N.V.
发明人： VAN DEN HAMER, Peter , HOLLMANN, Hendrik, D., L. , BODLAENDER, Maarten, P.
IPC分类号： G06K19/07
CPC分类号： G06K19/07 , G06F17/218 , G06F17/2258 , G06F17/271 , G06F17/3028
摘要： A data tag containing self-descriptive data, a method for reading such a data tag and a system for interpreting such a data tag are disclosed. Characterizing information about a first data element (112) stored in a memory (310) of the data tag (300) is stored in a first header (110) preceding a first data element (112). In addition, characterizing information about a second data element (116) stored in the memory (310) of the data tag (300) is stored in a second header (114) preceding a second data element (318). The application of a multitude of descriptive headers, each characterizing a data element stored in the data tag memory (310), facilitates flexible data storage on such devices. Furthermore, it also facilitates data compression due to the fact that field lengths can be characterized as well, thus excluding the presence of redundant bits in the data stored in the memory (310).

8. 发明公开

EP1820309A2 STREAMING MEMORY CONTROLLER 有权
标题翻译：流媒体存储器控制器
公开(公告)号：EP1820309A2
公开(公告)日：2007-08-22
申请号：EP05850071.1
申请日：2005-11-30
申请人： Koninklijke Philips Electronics N.V.
发明人： BURCHARD, Artur , HEKSTRA-NOWACKA, Ewa , HARMSZE, Francoise, J. , VAN DEN HAMER, Peter
IPC分类号： H04L12/56
CPC分类号： H04L49/9063 , G06F13/1673 , H04L49/90
摘要： A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N). The memory controller (SMC) comprises a first interface (PI), a streaming memory unit (SMU) and a second interface (MI). The first interface (PI) is used for connecting the memory controller (SMC) to the network (N) for receiving and transmitting data streams (STl - ST4). The streaming memory unit (SMU) is coupled to the first interface (PI) for controlling data streams (STl - ST4) between the network (N) and the memory (MEM). The streaming memory unit (SMU) comprises a buffer (B) for temporarily storing at least part of the data streams (STl - ST4) and a buffer managing unit (BMU) for managing the temporarily storing of the data streams (STl - ST4) in the buffer (B). The second interlace (MI) is coupled to the streaming memory unit (SMU) for connecting the memory controller (SMC) to the memory (MEM) in order to exchange data with the memory (MEM) in bursts. The streaming memory unit (SMU) is provided to implement network services of the network (N) onto the memory (MEM).
摘要翻译：存储器控制器（SMC）被提供用于将存储器（MEM）耦合到网络（N）。存储器控制器（SMC）包括第一接口（PI），流式存储器单元（SMU）和第二接口（MI）。第一接口（PI）用于将存储器控制器（SMC）连接到网络（N）以接收和发送数据流（ST1-ST4）。流式存储器单元（SMU）耦合到第一接口（PI），用于控制网络（N）和存储器（MEM）之间的数据流（ST1-ST4）。流式存储器单元（SMU）包括用于临时存储数据流（ST1-ST4）的至少一部分的缓冲器（B）和用于管理数据流（ST1-ST4）的临时存储的缓冲器管理单元（BMU）在缓冲区（B）中。第二交织（MI）耦合到流式存储器单元（SMU），用于将存储器控制器（SMC）连接到存储器（MEM）以便以突发形式与存储器（MEM）交换数据。提供流存储器单元（SMU）以将网络（N）的网络服务实现到存储器（MEM）上。

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