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1. 发明申请

US20090115502A1 REFERENCE CURRENT CIRCUIT, REFERENCE VOLTAGE CIRCUIT, AND STARTUP CIRCUIT 有权
标题翻译：参考电流电路，参考电压电路和启动电路
公开(公告)号：US20090115502A1
公开(公告)日：2009-05-07
申请号：US12093393
申请日：2007-09-04
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译：电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。从电流镜电路10输出的两个电流分别分配给两个。在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。这轻而易举地减少了四分之一的必要阻力。

2. 发明授权

US07808307B2 Reference current circuit, reference voltage circuit, and startup circuit 有权
标题翻译：参考电流电路，参考电压电路和启动电路
公开(公告)号：US07808307B2
公开(公告)日：2010-10-05
申请号：US12093393
申请日：2007-09-04
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Masayoshi Kinoshita
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.
摘要翻译：电流镜电路10形成为具有1：m的电流比（晶体管尺寸比）。同样，各对nMOS晶体管MN1，MN3和nMOS晶体管MN2，MN4形成为具有1：m的电流比。从电流镜电路10输出的两个电流分别分配给两个。在nMOS晶体管MN2，MN4中流动的分布电流相加，然后被允许流入一个电阻器R2。因此，对于电阻器R2，例如当m = 1时，只有一个双电流的电流就足够了。这轻而易举地减少了四分之一的必要阻力。

3. 发明申请

US20080315933A1 PULSE SYNTHESIS CIRCUIT 有权
标题翻译：脉冲合成电路
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

4. 发明申请

US20080007243A1 Reference voltage generation circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20080007243A1
公开(公告)日：2008-01-10
申请号：US11783800
申请日：2007-04-12
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A reference voltage generation circuit of the present invention includes: a band gap reference-type current generation circuit for controlling each of currents flowing through a first current path and a second current path, which are extending from a first node to a second node, to be a predetermined reference current, by utilizing a voltage difference occurring between a pair of transistors or diodes; and a resistive load circuit provided between the second node and a third node.
摘要翻译：本发明的参考电压产生电路包括：带隙基准电流产生电路，用于控制从第一节点延伸到第二节点的流过第一电流路径和第二电流路径的每个电流到通过利用在一对晶体管或二极管之间出现的电压差来作为预定的参考电流; 以及设置在第二节点和第三节点之间的电阻性负载电路。

5. 发明授权

US07812637B2 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US07812637B2
公开(公告)日：2010-10-12
申请号：US12510718
申请日：2009-07-28
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
摘要翻译：输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

6. 发明申请

US20080191743A1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US20080191743A1
公开(公告)日：2008-08-14
申请号：US11976671
申请日：2007-10-26
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K3/35613
摘要： Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
摘要翻译：输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

7. 发明授权

US07920002B2 Pulse synthesis circuit 有权
标题翻译：脉冲合成电路
公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

8. 发明申请

US20090284282A1 LEVEL SHIFTER 有权
标题翻译：水平变化
公开(公告)号：US20090284282A1
公开(公告)日：2009-11-19
申请号：US12510718
申请日：2009-07-28
申请人： Akinori MATSUMOTO , Shiro Sakiyama , Takashi Morie
发明人： Akinori MATSUMOTO , Shiro Sakiyama , Takashi Morie
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K3/35613
摘要： Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
摘要翻译：输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

9. 发明授权

US08130608B2 Coupled ring oscillator and method for initializing the same 有权
标题翻译：耦合环形振荡器及其初始化方法
公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B7/00 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

10. 发明申请

US20110080821A1 COUPLED RING OSCILLATOR AND METHOD FOR INITIALIZING THE SAME 有权
标题翻译：耦合振荡器及其初始化方法
公开(公告)号：US20110080821A1
公开(公告)日：2011-04-07
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B20/10 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

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