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1. 发明授权

US08435888B2 Semiconductor device and the method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08435888B2
公开(公告)日：2013-05-07
申请号：US13329712
申请日：2011-12-19
申请人： Koji Sasaki , Kazuo Matsuzaki , Takashi Kobayashi
发明人： Koji Sasaki , Kazuo Matsuzaki , Takashi Kobayashi
IPC分类号： H01L21/44
CPC分类号： H01L24/04 , H01L24/03 , H01L24/48 , H01L2224/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01045 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.
摘要翻译：半导体器件包括半导体衬底; 在所述半导体基板上的金属电极布线层压体，所述金属电极布线层叠体以预定的布线图案形成图案; 所述金属电极布线层压体包括底涂阻隔金属层压体和铝或铝合金膜在所述底涂层阻挡金属层压板上; 以及覆盖所述金属电极布线层叠体的有机钝化膜，其中所述阻挡金属层叠体为包含夹在氮化钛膜中的钛膜的三层层叠体。根据本发明的半导体器件有助于提高在制造过程中暂时暴露的阻挡金属层叠体的部分的耐湿性，仅使用一个钝化膜，有助于防止由裂纹引起的故障和由Si结节引起的故障留在铝合金中增加。

2. 发明申请

US20120088364A1 SEMICONDUCTOR DEVICE AND THE METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120088364A1
公开(公告)日：2012-04-12
申请号：US13329712
申请日：2011-12-19
申请人： Koji SASAKI , Kazuo Matsuzaki , Takashi Kobayashi
发明人： Koji SASAKI , Kazuo Matsuzaki , Takashi Kobayashi
IPC分类号： H01L21/768
CPC分类号： H01L24/04 , H01L24/03 , H01L24/48 , H01L2224/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01045 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.
摘要翻译：半导体器件包括半导体衬底; 在所述半导体基板上的金属电极布线层压体，所述金属电极布线层叠体以预定的布线图案形成图案; 所述金属电极布线层压体包括底涂阻隔金属层压体和铝或铝合金膜在所述底涂层阻挡金属层压板上; 以及覆盖所述金属电极布线层叠体的有机钝化膜，其中所述阻挡金属层叠体为包含夹在氮化钛膜中的钛膜的三层层叠体。根据本发明的半导体器件有助于提高在制造过程中暂时暴露的阻挡金属层叠体的部分的耐湿性，仅使用一个钝化膜，有助于防止由裂纹引起的故障和由Si结节引起的故障留在铝合金中增加。

3. 发明授权

US08102050B2 Semiconductor device and the method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08102050B2
公开(公告)日：2012-01-24
申请号：US12243477
申请日：2008-10-01
申请人： Koji Sasaki , Kazuo Matsuzaki , Takashi Kobayashi
发明人： Koji Sasaki , Kazuo Matsuzaki , Takashi Kobayashi
IPC分类号： H01L23/48
CPC分类号： H01L24/04 , H01L24/03 , H01L24/48 , H01L2224/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01033 , H01L2924/01045 , H01L2924/0105 , H01L2924/01061 , H01L2924/01074 , H01L2924/04941 , H01L2924/10253 , H01L2924/14 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor substrate; a metal electrode wiring laminate on the semiconductor substrate, the metal electrode wiring laminate being patterned with a predetermined wiring pattern; the metal electrode wiring laminate including an undercoating barrier metal laminate and aluminum or aluminum alloy film on the undercoating barrier metal laminate; and organic passivation film covering the metal electrode wiring laminate, wherein the barrier metal laminate is a three-layered laminate including titanium films sandwiching a titanium nitride film. The semiconductor device according to the invention facilitates improving the moisture resistance of the portion of the barrier metal laminate exposed temporarily in the manufacturing process, facilitates employing only one passivation film, facilitates preventing the failures caused by cracks from occurring and the failures caused by Si nodules remaining in the aluminum alloy from increasing.
摘要翻译：半导体器件包括半导体衬底; 在所述半导体基板上的金属电极布线层压体，所述金属电极布线层叠体以预定的布线图案形成图案; 所述金属电极布线层压体包括底涂阻隔金属层压体和铝或铝合金膜在所述底涂层阻挡金属层压板上; 以及覆盖所述金属电极布线层叠体的有机钝化膜，其中所述阻挡金属层压体为包含夹着氮化钛膜的钛膜的三层层叠体。根据本发明的半导体器件有助于提高在制造过程中暂时暴露的阻挡金属层叠体的部分的耐湿性，仅使用一个钝化膜，有助于防止由裂纹引起的故障和由Si结节引起的故障留在铝合金中增加。

4. 发明授权

US07521757B2 Semiconductor device with back surface electrode including a stress relaxation film 有权
标题翻译：具有包括应力松弛膜的背面电极的半导体装置
公开(公告)号：US07521757B2
公开(公告)日：2009-04-21
申请号：US11812810
申请日：2007-06-21
申请人： Takashi Kobayashi , Koji Sasaki , Yasuharu Mikoshiba , Masahiro Kato
发明人： Takashi Kobayashi , Koji Sasaki , Yasuharu Mikoshiba , Masahiro Kato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/41708 , H01L29/0834 , H01L29/66333 , H01L29/7395 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13055 , H01L2924/13091
摘要： A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 μm; an outermost metal film; and a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film so that false judgment of chip quality based on leakage current measurements during manufacturing is reduced particularly when dust is present and skews leakage current measurements due to strain on the wafer and the piezoelectric effect produced.
摘要翻译：半导体器件包括具有第一和第二主表面区域的半导体衬底; 绝缘栅结构，其形成在所述第一主表面区域中; 背面区域半导体层，其形成在所述第二主面区域中，并且具有至多5μm的厚度; 最外面的金属膜; 以及背面电极，其形成在背面区域半导体层和最外层金属膜之间的第二主面区域中，并且由层叠的多个膜构成，并且包括应力松弛膜，从而使芯片的错误判断基于制造期间的漏电流测量的质量特别地降低，特别是当存在灰尘并且由于晶片上的应变和产生的压电效应而偏移泄漏电流测量。

5. 发明申请

US20080006856A1 Semiconductor device with back surface electrode including a stress relaxation film 有权
标题翻译：具有包括应力松弛膜的背面电极的半导体装置
公开(公告)号：US20080006856A1
公开(公告)日：2008-01-10
申请号：US11812810
申请日：2007-06-21
申请人： Takashi Kobayashi , Koji Sasaki , Yasuharu Mikoshiba , Masahiro Kato
发明人： Takashi Kobayashi , Koji Sasaki , Yasuharu Mikoshiba , Masahiro Kato
IPC分类号： H01L29/76 , H01L27/082
CPC分类号： H01L29/41708 , H01L29/0834 , H01L29/66333 , H01L29/7395 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/13055 , H01L2924/13091
摘要： A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 μm; an outermost metal film; and a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film so that false judgment of chip quality based on leakage current measurements during manufacturing is reduced particularly when dust is present and skews leakage current measurements due to strain on the wafer and the piezoelectric effect produced.
摘要翻译：半导体器件包括具有第一和第二主表面区域的半导体衬底; 绝缘栅结构，其形成在所述第一主表面区域中; 背面区域半导体层，其形成在所述第二主面区域中，并且具有至多5μm的厚度; 最外面的金属膜; 以及背面电极，其形成在背面区域半导体层和最外层金属膜之间的第二主面区域中，并且由层叠的多个膜构成，并且包括应力松弛膜，从而使芯片的错误判断基于制造期间的漏电流测量的质量特别地降低，特别是当存在灰尘并且由于晶片上的应变和产生的压电效应而偏移泄漏电流测量。

6. 发明授权

US10077485B2 Steel sheet for soft-nitriding and method for manufacturing the same 有权
公开(公告)号：US10077485B2
公开(公告)日：2018-09-18
申请号：US14409549
申请日：2012-06-27
申请人： Takashi Kobayashi , Nobuyuki Nakamura , Yoshimasa Funakawa
发明人： Takashi Kobayashi , Nobuyuki Nakamura , Yoshimasa Funakawa
IPC分类号： C22C38/26 , C21D6/00 , C22C38/00 , C22C38/06 , C22C38/04 , C21D9/46 , C21D8/02 , C22C38/02 , C22C38/24 , C22C38/38 , C23C8/26
CPC分类号： C21D9/46 , C21D6/002 , C21D6/005 , C21D6/008 , C21D8/0226 , C21D8/0263 , C21D2211/005 , C21D2211/009 , C22C38/00 , C22C38/001 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/24 , C22C38/26 , C22C38/38 , C23C8/26
摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; V: 0.03% or more to 0.30% or less; and N: 0.005% or less, on a mass percent basis, wherein a ratio of amount of solute V to the V content (amount of solute V/V content) is more than 0.50, and balance comprises Fe and incidental impurities, and a complex-phase microstructure containing ferrite and pearlite.

7. 发明申请

US20150299830A1 STEEL SHEET FOR SOFT-NITRIDING AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：用于软土的钢板及其制造方法
公开(公告)号：US20150299830A1
公开(公告)日：2015-10-22
申请号：US14408662
申请日：2012-06-27
申请人： Takashi Kobayashi , Nobuyuki Nakamura , Tetsuya Mega
发明人： Takashi Kobayashi , Nobuyuki Nakamura , Tetsuya Mega
IPC分类号： C22C38/26 , C21D9/46 , C22C38/00 , C22C38/06 , C22C38/04 , C22C38/02 , C21D8/02 , C21D6/00
CPC分类号： C22C38/26 , C21D6/002 , C21D6/005 , C21D6/008 , C21D8/0263 , C21D9/46 , C21D2211/005 , C21D2211/009 , C22C38/00 , C22C38/001 , C22C38/002 , C22C38/02 , C22C38/04 , C22C38/06 , C23C8/32
摘要： A steel sheet for soft-nitriding has a composition containing: C: 0.05% or more to 0.10% or less; Si: 0.5% or less; Mn: 0.7% or more to 1.5% or less; P: 0.05% or less; S: 0.01% or less; Al: 0.01% or more to 0.06% or less; Cr: 0.5% or more to 1.5% or less; Nb: 0.005% or more to 0.025% or less; and N: 0.005% or less, on a mass percent basis, such that C and Nb satisfy 0.10≦Nb/C≦0.30 (where C and Nb are respective contents of the elements (by mass %)), wherein balance comprises Fe and incidental impurities, and a microstructure that is a complex-phase microstructure containing ferrite and pearlite, and the microstructure having a ratio of a microstructure other than the ferrite and the pearlite of 1% or less, and the microstructure having a ratio of polygonal ferrite in the ferrite of less than 50%.
摘要翻译：软氮化钢板的组成为：C：0.05％以上且0.10％以下， Si：0.5％以下; Mn：0.7％以上至1.5％以下; P：0.05％以下; S：0.01％以下; Al：0.01％以上至0.06％以下; Cr：0.5％以上至1.5％以下; Nb：0.005％以上至0.025％以下; 和N：0.005％以下，C和Nb满足0.10＆nlE; Nb / C＆lt; NlE; 0.30（其中，C和Nb分别为元素含量（质量％）），其中余量包含Fe 和杂质，以及包含铁素体和珠光体的复相组织的显微组织以及具有1％以下的铁素体和珠光体以外的组织比的微结构，以及具有多边形铁素体在铁素体中小于50％。

8. 发明授权

US08866123B2 Non-volatile memory device and production method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08866123B2
公开(公告)日：2014-10-21
申请号：US13884331
申请日：2010-11-22
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Takahiro Morikawa , Akio Shima , Takashi Kobayashi
IPC分类号： H01L47/00 , H01L45/00 , H01L29/792 , H01L27/24 , H01L29/66 , H01L27/115
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
摘要翻译：垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接双层选择晶体管。利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

9. 发明授权

US08835872B2 Sample stage device 有权
标题翻译：样品台装置
公开(公告)号：US08835872B2
公开(公告)日：2014-09-16
申请号：US13806989
申请日：2011-06-23
申请人： Takashi Kobayashi
发明人： Takashi Kobayashi
IPC分类号： H01J37/20
CPC分类号： H01J37/20 , H01J2237/20285 , H01J2237/20292 , H01J2237/2817 , H01L21/68
摘要： A sample stage device (10) is so configured as to calculate ideal position information xtg(i), tg(i) per predetermined period that is unaffected by drive conditions relating to gaps (25, 26), etc., and to determine, per predetermined cycle and in real time, deviations dx(i), dy(i) between real-time measured positions x(i), y(i) by position detectors comprising laser interferometers (33, 34), etc., and ideal position information xtg(i), tg(i). In addition, it calculates, based on deviations dx(i), dy(i) thus determined, such speed command values vx(i), vy(i) for motors (27, 28) that measured values x(i), y(i) would follow ideal position information xtg(i), tg(i), and performs stable and high-speed positioning control for a sample table (11) through feedback control that controls speed in real time. Thus, with respect to a sample stage device, it is possible to provide a stable and high-speed positioning control method for a sample table, which is capable of suppressing noise caused by thermal drift and vibration, without being affected by drive conditions, such as the initial states of gaps, etc.
摘要翻译：样品台装置（10）被配置为计算不受与间隙（25,26）等有关的驱动条件的影响的每预定周期的理想位置信息xtg（i），tg（i）并且实时地通过包括激光干涉仪（33,34）的位置检测器等实时测量位置x（i），y（i）之间的偏差dx（i），dy（i）和理想位置信息xtg（i），tg（i）。另外，根据如此确定的偏差dx（i），dy（i），计算出测量值x（i），y（i）的电动机（27,28）的速度指令值vx（i），vy （i）将遵循理想位置信息xtg（i），tg（i），并且通过实时控制速度的反馈控制对样本表（11）执行稳定和高速定位控制。因此，对于样品台装置，可以提供一种用于样品台的稳定且高速的定位控制方法，其能够抑制由热漂移和振动引起的噪声，而不受驱动条件的影响，例如作为差距的初始状态等

10. 发明授权

US08772746B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08772746B2
公开(公告)日：2014-07-08
申请号：US13349653
申请日：2012-01-13
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2454 , H01L27/2472 , H01L45/144 , H01L45/1675
摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.
摘要翻译：可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和电阻变化元件的一部分设置在多条字线的上方。这样的配置可以减小单元面积并确保设计自由度。

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