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1. 发明申请

US20070211746A1 INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND DATA COMMUNICATION METHOD 有权
标题翻译：信息处理装置，信息处理系统和数据通信方法
公开(公告)号：US20070211746A1
公开(公告)日：2007-09-13
申请号：US11684229
申请日：2007-03-09
申请人： Koji OSHIKIRI , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
发明人： Koji OSHIKIRI , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
IPC分类号： H04J3/16
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.
摘要翻译：高速串行交换结构被配置为执行能够将业务区分到虚拟信道上的业务类别的映射。高速串行交换矩阵连接多个设备。当与连接到高速串行交换机结构的设备之间发生冲突时，流量级设置单元设置具有冲突的设备中的每个业务的业务等级。信道设置单元将每个设置的业务类别分配给不同的虚拟信道，并且给予每个设置业务类别的数据通信的优先级。

2. 发明授权

US07698484B2 Information processor configured to detect available space in a storage in another information processor 有权
标题翻译：配置为检测另一信息处理器中的存储器中的可用空间的信息处理器
公开(公告)号：US07698484B2
公开(公告)日：2010-04-13
申请号：US11523054
申请日：2006-09-19
申请人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
发明人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
IPC分类号： G06F13/00 , G06F3/00 , G06F15/173
CPC分类号： G06F9/5016 , G06F9/468
摘要： An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.
摘要翻译：经由网络连接至少一个其它信息处理器的信息处理器包括：检测单元，其检测用于信息处理的可选设备，作为安装在另一个信息处理器上的目标可选设备;发布单元，向另一个信息处理器发出使用目标可选设备的访问请求;接收单元，其从其他信息处理器接收对目标可选设备的访问许可;以及处理单元，其执行与目标可选的信息处理设备。

3. 发明授权

US07664904B2 High speed serial switch fabric performing mapping of traffic classes onto virtual channels 有权
标题翻译：高速串行交换矩阵，将流量分类映射到虚拟通道
公开(公告)号：US07664904B2
公开(公告)日：2010-02-16
申请号：US11684229
申请日：2007-03-09
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.
摘要翻译：高速串行交换结构被配置为执行能够将业务区分到虚拟信道上的业务类别的映射。高速串行交换矩阵连接多个设备。当与连接到高速串行交换机结构的设备之间发生冲突时，流量级设置单元设置具有冲突的设备中的每个业务的业务等级。信道设置单元将每个设置的业务类别分配给不同的虚拟信道，并且给予每个设置业务类别的数据通信的优先级。

4. 发明申请

US20070067551A1 Information processor 有权
标题翻译：信息处理器
公开(公告)号：US20070067551A1
公开(公告)日：2007-03-22
申请号：US11523054
申请日：2006-09-19
申请人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
发明人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
IPC分类号： G06F13/36
CPC分类号： G06F9/5016 , G06F9/468
摘要： An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.
摘要翻译：经由网络连接至少一个其它信息处理器的信息处理器包括：检测单元，其检测用于信息处理的可选设备，作为安装在另一个信息处理器上的目标可选设备;发布单元，向另一个信息处理器发出使用目标可选设备的访问请求;接收单元，其从其他信息处理器接收对目标可选设备的访问许可;以及处理单元，其执行与目标可选的信息处理设备。

5. 发明授权

US5828384A Image display control device, method and computer program product 失效
标题翻译：图像显示控制装置，方法和计算机程序产品
公开(公告)号：US5828384A
公开(公告)日：1998-10-27
申请号：US711870
申请日：1996-09-12
申请人： Keiichi Iwasaki , Toshihiro Tsukagoshi
发明人： Keiichi Iwasaki , Toshihiro Tsukagoshi
IPC分类号： G09G5/34 , G09G5/395 , G09G5/399 , G09G5/42 , G09G5/00
CPC分类号： G09G5/395 , G09G5/399 , G09G2340/12 , G09G5/42
摘要： A VRAM stores a plurality of patterns of image data, an offset register stores values which indicate definition starting positions from which display image data are defined from the plurality of patterns of image data, respectively, a horizontal counter counts dots in a horizontal scanning direction, and a vertical counter counts lines in vertical scanning direction. Address and control signals are successively provided for reading a respective line of the display image data from the VRAM within one horizontal scanning period, based on the values of the offset register and the value of the vertical counter. Each of two second storage devices has a storage capacity for storing a thus-read respective line of the image data. Thus-read image data is written at addresses of a predetermined one of the two second storage devices, the addresses corresponding to displaying dots of the image data, while, according to the value of the horizontal counter, image data stored in the other one of the two second storage devices is read out, where, the image data writing and reading operations are performed alternately between the two second storage devices for each horizontal scanning period.
摘要翻译： VRAM存储多个图像数据图案，偏移寄存器分别存储指示从多个图像数据图案定义显示图像数据的定义开始位置的值，水平计数器对水平扫描方向计数点，并且垂直计数器在垂直扫描方向上对行进行计数。连续地提供地址和控制信号，用于基于偏移寄存器的值和垂直计数器的值，在一个水平扫描周期内从VRAM读取显示图像数据的相应行。两个第二存储装置中的每一个具有用于存储如此读取的图像数据的相应行的存储容量。这样读取的图像数据被写入两个第二存储装置中的预定的一个的地址，对应于显示图像数据的点的地址，而根据水平计数器的值，存储在另一个中的图像数据读出两个第二存储装置，其中在每个水平扫描周期中，在两个第二存储装置之间交替地执行图像数据写入和读取操作。

6. 发明授权

US09396789B2 Memory control device and a delay controller 有权
标题翻译：存储控制装置和延迟控制器
公开(公告)号：US09396789B2
公开(公告)日：2016-07-19
申请号：US14879925
申请日：2015-10-09
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G11C11/4096 , G11C11/40 , G11C11/406 , G11C11/4076 , G06F13/42 , G11C7/04 , G11C7/22
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/42 , G11C7/04 , G11C7/222 , G11C11/406 , G11C11/40611 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
摘要翻译：存储器控制装置包括多个延迟电路，用于为存储器的每个端子设置延迟值，多个延迟电路中的每一个连接到存储器的端子。此外，存储器控制装置包括：第一寄存器，用于存储由延迟锁定环电路输出的第一DLL值，多个第二寄存器，用于存储第一设定值以设置存储器的每个端子的延迟值，所述多个第二寄存器连接到所述多个延迟电路的延迟电路，以及延迟控制器，用于基于所述第一DLL值计算第二设定值，所述延迟控制器基于所述第一DLL值，所述延迟锁定环电路在所述第一DLL之后输出的第二DLL值值和第一设定值，并将第一设定值更新为第二设定值。

7. 发明授权

US08432754B2 Memory control apparatus and mask timing adjusting method 有权
标题翻译：存储器控制装置和掩模定时调整方法
公开(公告)号：US08432754B2
公开(公告)日：2013-04-30
申请号：US13049695
申请日：2011-03-16
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C29/02 , G11C29/028 , G11C29/50012
摘要： A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.
摘要翻译：一种公开的同步存储器控制装置，用于与来自存储器电路的选通信号同步地从存储器电路读取的数据的接收包括使用掩码信号屏蔽选通信号的掩模电路; 定时测量电路延迟所述延迟选通信号中的每一个的延迟和锁存数据的多个单元中的选通信号; 以及产生掩模信号的掩模产生电路。定时测量电路在对应的屏蔽选通信号的第一个上升沿锁存每个延迟选通信号的数据。掩模生成电路包括具有多个延迟单位的延迟电路。屏蔽信号的开始定时与内部时钟同步地被调整，并且输出具有与延迟电路的所选择的延迟单位对应的延迟量的信号作为掩码信号。

8. 发明授权

US07161854B2 Jitter and skew suppressing delay control apparatus 有权
标题翻译：抖动抑制延迟控制装置
公开(公告)号：US07161854B2
公开(公告)日：2007-01-09
申请号：US11167627
申请日：2005-06-27
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G11C7/00
CPC分类号： H03L7/0814 , G11C7/1072 , G11C7/222 , H03L7/07 , H03L7/0805
摘要： A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.
摘要翻译：延迟控制装置包括第一和第二延迟元件，每个延迟元件被配置为接收和延迟选通信号和时钟预定的延迟值。提供规定数量的触发器，用于在接收到从第二延迟元件输出的选通信号时输入数据。当选择装置选择选通信号时，第二延迟元件将选通信号延迟并输出到触发器。相位比较器比较从第一和第二延迟元件输出的时钟。当选择装置选择时钟时，延迟控制装置根据相位比较器的比较结果改变第二延迟元件的规定延迟值。

9. 发明授权

US5870074A Image display control device, method and computer program product 失效
标题翻译：图像显示控制装置，方法和计算机程序产品
公开(公告)号：US5870074A
公开(公告)日：1999-02-09
申请号：US747886
申请日：1996-11-13
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G09G5/18 , G09G5/30 , G09G5/32 , G09G5/377 , G09G5/38 , G09G5/42 , G09G5/22 , G09G5/26
CPC分类号： G09G5/42
摘要： A character table unit stores as attribute data of each character of an image a character name, a horizontal direction character size, a vertical direction character size, a horizontal display coordinate value and, a vertical display coordinate. A counter outputs count values indicating a horizontal position and a vertical position in a display screen image. A first writing control unit reads from the character table unit the attribute data of an appropriate character based on the count values of the counter and the attribute data, produces basic size attribute data of basic size characters which constitute at least part of the character. The basic size character is determined to be currently displayed based on the count values. The basic size character attribute data is written in a hit buffer. A image data memory stores character image data. A second writing control unit reads basic size attribute data from the hit buffer, producing addresses based on the basic size attribute data to read character image data from the image data memory, and writing the character image data into a line buffer. Image data is read from the line buffer, in synchronization with the count value indicating a current horizontal position.
摘要翻译：字符表单元将图像的每个字符的属性数据作为字符名称，水平方向字符尺寸，垂直方向字符尺寸，水平显示坐标值和垂直显示坐标存储。计数器输出指示显示画面图像中的水平位置和垂直位置的计数值。第一写入控制单元基于计数器和属性数据的计数值从字符表单元读取适当字符的属性数据，生成构成字符的至少一部分的基本大小字符的基本大小属性数据。根据计数值确定当前显示的基本尺寸字符。基本大小字符属性数据写入命中缓冲区。图像数据存储器存储字符图像数据。第二写入控制单元从命中缓冲器读取基本大小属性数据，根据基本尺寸属性数据产生地址，以从图像数据存储器读取字符图像数据，并将字符图像数据写入行缓冲器。与指示当前水平位置的计数值同步地从行缓冲器读取图像数据。

10. 发明授权

US07671919B2 Camera 失效
标题翻译：相机
公开(公告)号：US07671919B2
公开(公告)日：2010-03-02
申请号：US11072561
申请日：2005-03-04
申请人： Keiichi Iwasaki , Yukimasa Yamaguchi , Kiyoshi Nakagawa
发明人： Keiichi Iwasaki , Yukimasa Yamaguchi , Kiyoshi Nakagawa
IPC分类号： H04N5/225 , G03B17/02
CPC分类号： H04N5/2254 , B60R1/00 , B60R2001/1253 , B60R2300/103 , B60R2300/105 , B60R2300/106 , B60R2300/207 , B60R2300/8013 , B60R2300/802 , B60R2300/8053 , B60R2300/8066 , B60R2300/8073
摘要： First to fourth lenses are aligned in an optical axis direction by a lens-barrel of a camera, an O-ring is disposed between the first lens and the lens-barrel, an O-ring is disposed between the fourth lens and the lens-barrel, a space is formed between the first and second lenses, a space is formed between the second and fourth lenses, a space is formed between the third and fourth lenses, and flow of air between the spaces is precluded. The camera thus configured is free of dewing on the lens or a protective plate exposed to the exterior, even when the inside temperature is raised due to heat generation in a CCD or a mounting substrate on which the CCD is mounted.
摘要翻译：第一至第四透镜通过相机的透镜镜筒在光轴方向上对准，O形环设置在第一透镜和透镜镜筒之间，O形环设置在第四透镜和透镜镜筒之间，在第一透镜和第二透镜之间形成空间，在第二透镜和第四透镜之间形成空间，在第三透镜和第四透镜之间形成空间，并且排除空间之间的空气流动。因此，即使在CCD或安装有CCD的安装基板上的发热引起内部温度上升的情况下，由此构成的相机也不会在透镜上露出或者暴露于外部的保护板。

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