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1. 发明申请

US20160035408A1 MEMORY CONTROL DEVICE AND A DELAY CONTROLLER 有权
标题翻译：存储控制装置和延迟控制器
公开(公告)号：US20160035408A1
公开(公告)日：2016-02-04
申请号：US14879925
申请日：2015-10-09
申请人： Keiichi IWASAKI
发明人： Keiichi IWASAKI
IPC分类号： G11C11/4076 , G11C11/4096 , G11C11/406
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/42 , G11C7/04 , G11C7/222 , G11C11/406 , G11C11/40611 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
摘要翻译：存储器控制装置包括多个延迟电路，用于为存储器的每个端子设置延迟值，多个延迟电路中的每一个连接到存储器的端子。此外，存储器控制装置包括：第一寄存器，用于存储由延迟锁定环电路输出的第一DLL值，多个第二寄存器，用于存储第一设定值以设置存储器的每个端子的延迟值，所述多个第二寄存器连接到所述多个延迟电路的延迟电路，以及延迟控制器，用于基于所述第一DLL值计算第二设置值，所述延迟控制器基于所述第一DLL值，所述延迟锁定环电路在所述第一DLL之后输出的第二DLL值值和第一设定值，并将第一设定值更新为第二设定值。

2. 发明授权

US07664904B2 High speed serial switch fabric performing mapping of traffic classes onto virtual channels 有权
标题翻译：高速串行交换矩阵，将流量分类映射到虚拟通道
公开(公告)号：US07664904B2
公开(公告)日：2010-02-16
申请号：US11684229
申请日：2007-03-09
申请人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
发明人： Koji Oshikiri , Noriyuki Terao , Junichi Ikeda , Atsuhiro Oizumi , Satoru Numakura , Yutaka Maita , Tomonori Tanaka , Hiroyuki Kimbara , Keiichi Iwasaki , Toshihiro Tsukagoshi , Iwao Hamaguchi , Hidetake Tanaka , Naoki Tsumura , Hiroo Kitagawa
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.
摘要翻译：高速串行交换结构被配置为执行能够将业务区分到虚拟信道上的业务类别的映射。高速串行交换矩阵连接多个设备。当与连接到高速串行交换机结构的设备之间发生冲突时，流量级设置单元设置具有冲突的设备中的每个业务的业务等级。信道设置单元将每个设置的业务类别分配给不同的虚拟信道，并且给予每个设置业务类别的数据通信的优先级。

3. 发明申请

US20080024883A1 Image pickup apparatus 失效
标题翻译：摄像设备
公开(公告)号：US20080024883A1
公开(公告)日：2008-01-31
申请号：US11825580
申请日：2007-07-06
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G02B7/02
CPC分类号： G02B7/022 , H04N5/2252 , H04N5/2253 , H04N5/2254
摘要： An image pickup apparatus includes a housing, a lens incorporated in the front of the housing and configured to constitute an imaging optical system, an image pickup device provided in the housing and configured to capture a subject image guided by the imaging optical system, a printed wiring board provided in the housing and having the image pickup device mounted thereon, a barrel provided integrally with the front of the housing, an annular lens cover configured to push a face of the lens facing forward in a rearward direction, and detachably mounted on the front of the barrel, and a support wall projecting rearward outside a rear end of the barrel in the radial direction and inside the housing, and bonded to the printed wiring board with adhesive.
摘要翻译：一种图像拾取装置，包括：外壳，并入外壳的前部并配置为构成成像光学系统的镜头;设置在外壳中并构造成捕获由成像光学系统引导的被摄体图像的图像拾取装置，设置在壳体中并具有安装在其上的图像拾取装置的线路板，与壳体的前部一体地设置的圆筒;环形透镜盖，构造成将透镜的面朝向后方推动，并且可拆卸地安装在并且在壳体的内侧在壳体的后端部向后方突出的支撑壁，并且利用粘合剂将其贴合于印刷电路板。

4. 发明申请

US20070067551A1 Information processor 有权
标题翻译：信息处理器
公开(公告)号：US20070067551A1
公开(公告)日：2007-03-22
申请号：US11523054
申请日：2006-09-19
申请人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
发明人： Junichi Ikeda , Koji Oshikiri , Noriyuki Terao , Atsuhiro Oizumi , Yutaka Maita , Satoru Numakura , Hiroo Kitagawa , Tomonori Tanaka , Hiroyuki Kimbara , Hidetake Tanaka , Iwao Hamaguchi , Keiichi Iwasaki , Toshihiro Tsukagoshi , Naoki Tsumura
IPC分类号： G06F13/36
CPC分类号： G06F9/5016 , G06F9/468
摘要： An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.
摘要翻译：经由网络连接至少一个其它信息处理器的信息处理器包括：检测单元，其检测用于信息处理的可选设备，作为安装在另一个信息处理器上的目标可选设备;发布单元，向另一个信息处理器发出使用目标可选设备的访问请求;接收单元，其从其他信息处理器接收对目标可选设备的访问许可;以及处理单元，其执行与目标可选的信息处理设备。

5. 发明申请

US20050206780A1 Camera 失效
标题翻译：相机
公开(公告)号：US20050206780A1
公开(公告)日：2005-09-22
申请号：US11072561
申请日：2005-03-04
申请人： Keiichi Iwasaki , Yukimasa Yamaguchi , Kiyoshi Nakagawa
发明人： Keiichi Iwasaki , Yukimasa Yamaguchi , Kiyoshi Nakagawa
IPC分类号： G02B7/02 , B60R1/00 , B60R1/06 , B60R1/12 , B60R11/04 , G03B17/08 , H04N5/225
CPC分类号： H04N5/2254 , B60R1/00 , B60R2001/1253 , B60R2300/103 , B60R2300/105 , B60R2300/106 , B60R2300/207 , B60R2300/8013 , B60R2300/802 , B60R2300/8053 , B60R2300/8066 , B60R2300/8073
摘要： First to fourth lenses are aligned in an optical axis direction by a lens-barrel of a camera, an O-ring is disposed between the first lens and the lens-barrel, an O-ring is disposed between the fourth lens and the lens-barrel, a space is formed between the first and second lenses, a space is formed between the second and fourth lenses, a space is formed between the third and fourth lenses, and flow of air between the spaces is precluded. The camera thus configured is free of dewing on the lens or a protective plate exposed to the exterior, even when the inside temperature is raised due to heat generation in a CCD or a mounting substrate on which the CCD is mounted.
摘要翻译：第一至第四透镜通过相机的透镜镜筒在光轴方向上对准，O形环设置在第一透镜和透镜镜筒之间，O形环设置在第四透镜和透镜镜筒之间，在第一透镜和第二透镜之间形成空间，在第二透镜和第四透镜之间形成空间，在第三透镜和第四透镜之间形成空间，并且排除空间之间的空气流动。因此，即使在CCD或安装有CCD的安装基板上的发热引起内部温度上升的情况下，由此构成的相机也不会在透镜上露出或者暴露于外部的保护板。

6. 发明授权

US5107278A Image forming apparatus 失效
标题翻译：图像形成装置
公开(公告)号：US5107278A
公开(公告)日：1992-04-21
申请号：US603958
申请日：1990-10-25
申请人： Kazuyuki Shimada , Yoshiharu Niito , Keiichi Iwasaki , Yukitoshi Kiya , Hideo Azumai , Takahiro Yagishita , Masayoshi Miyamoto
发明人： Kazuyuki Shimada , Yoshiharu Niito , Keiichi Iwasaki , Yukitoshi Kiya , Hideo Azumai , Takahiro Yagishita , Masayoshi Miyamoto
IPC分类号： B41J2/44 , B41J2/00 , G03G15/00 , G03G15/04 , G03G21/00 , H04N1/00 , H04N1/113
CPC分类号： H04N1/00031 , H04N1/00002 , H04N1/00045 , H04N1/00053 , H04N1/00063
摘要： An image forming apparatus includes an image forming part for forming an image described by a video signal on a recording sheet by carrying out an image forming operation which includes scans in main and sub scan directions, a storage part for storing test pattern data which describes at least one test pattern to be formed on the recording sheet, a generator for generating a generation interval of the video signal in the main and sub scan directions responsive to the test pattern data stored in the storage part, and a controller for controlling the image forming operation of the image forming part by supplying to the image forming part the video signal which describes an arbitrary test pattern and is generated based on the test pattern data read from the storage part with the generation interval generated by the generator.
摘要翻译：图像形成装置包括图像形成部件，用于通过执行包括主扫描和副扫描方向的扫描的图像形成操作来形成由记录纸上的视频信号描述的图像的图像形成部件，用于存储测试图案数据的存储部件，要在记录纸上形成的至少一个测试图形，用于根据存储在存储部分中的测试图形数据产生主扫描和副扫描方向的视频信号的产生间隔的发生器，以及用于控制图像形成通过向图像形成部分提供描述任意测试图案的视频信号并基于由发生器产生的产生间隔从存储部分读取的测试图案数据来生成图像形成部分的操作。

7. 发明授权

US4977414A Image forming apparatus 失效
标题翻译：图像形成装置
公开(公告)号：US4977414A
公开(公告)日：1990-12-11
申请号：US424388
申请日：1989-10-20
申请人： Kazuyuki Shimada , Yoshiharu Niito , Yikitoshi Kiya , Takahiro Yagishita , Masayoshi Miyamoto , Hideo Azumai , Keiichi Iwasaki
发明人： Kazuyuki Shimada , Yoshiharu Niito , Yikitoshi Kiya , Takahiro Yagishita , Masayoshi Miyamoto , Hideo Azumai , Keiichi Iwasaki
IPC分类号： B41J2/44 , G02B26/10 , G03G15/04 , G06K15/12 , H04N1/113 , H04N1/23
CPC分类号： G06K15/1204 , G06K15/1209 , G06K15/1223
摘要： An image forming apparatus includes a photosensitive drum, a laser diode, and an optical scanning system provided between said laser diode and the photosensitive drum, for scanning the recording medium by deflecting the light beam emitted from the laser diode to thereby form an image on the recording medium. The optical scanning system has one of predetermined optical characteristics different from each other. The apparatus further includes a memory which stores a plurality of sets of control data provided for the predetermined optical characteristics of the optical scanning system. The control data is used for controlling the laser diode. Further, the apparatus includes a control data selecting circuit which selects one of the sets of control data which relates to the one of the predetermined optical characteristics of the optical scanning system, and a controller for controlling the laser diode on the basis of image data and the selected one of the sets of control data.
摘要翻译：图像形成装置包括感光鼓，激光二极管和设置在所述激光二极管和感光鼓之间的光学扫描系统，用于通过偏转从激光二极管发射的光束来扫描记录介质，从而在记录介质。光学扫描系统具有彼此不同的预定光学特性之一。该装置还包括存储器，其存储为光学扫描系统的预定光学特性提供的多组控制数据。控制数据用于控制激光二极管。此外，该装置包括控制数据选择电路，该控制数据选择电路选择与光学扫描系统的预定光学特性之一相关的控制数据组中的一个，以及基于图像数据控制激光二极管的控制器，所选择的一组控制数据。

8. 发明授权

US09396789B2 Memory control device and a delay controller 有权
标题翻译：存储控制装置和延迟控制器
公开(公告)号：US09396789B2
公开(公告)日：2016-07-19
申请号：US14879925
申请日：2015-10-09
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G11C11/4096 , G11C11/40 , G11C11/406 , G11C11/4076 , G06F13/42 , G11C7/04 , G11C7/22
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/42 , G11C7/04 , G11C7/222 , G11C11/406 , G11C11/40611 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
摘要翻译：存储器控制装置包括多个延迟电路，用于为存储器的每个端子设置延迟值，多个延迟电路中的每一个连接到存储器的端子。此外，存储器控制装置包括：第一寄存器，用于存储由延迟锁定环电路输出的第一DLL值，多个第二寄存器，用于存储第一设定值以设置存储器的每个端子的延迟值，所述多个第二寄存器连接到所述多个延迟电路的延迟电路，以及延迟控制器，用于基于所述第一DLL值计算第二设定值，所述延迟控制器基于所述第一DLL值，所述延迟锁定环电路在所述第一DLL之后输出的第二DLL值值和第一设定值，并将第一设定值更新为第二设定值。

9. 发明申请

US20140362653A1 MEMORY CONTROL DEVICE AND A DELAY CONTROLLER 审中-公开
标题翻译：存储控制装置和延迟控制器
公开(公告)号：US20140362653A1
公开(公告)日：2014-12-11
申请号：US14302044
申请日：2014-06-11
申请人： Keiichi IWASAKI
发明人： Keiichi IWASAKI
IPC分类号： G11C11/4063
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/42 , G11C7/04 , G11C7/222 , G11C11/406 , G11C11/40611 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
摘要翻译：存储器控制装置包括多个延迟电路，用于为存储器的每个端子设置延迟值，多个延迟电路中的每一个连接到存储器的端子。此外，存储器控制装置包括：第一寄存器，用于存储由延迟锁定环电路输出的第一DLL值，多个第二寄存器，用于存储第一设定值以设置存储器的每个端子的延迟值，所述多个第二寄存器连接到所述多个延迟电路的延迟电路，以及延迟控制器，用于基于所述第一DLL值计算第二设置值，所述延迟控制器基于所述第一DLL值，所述延迟锁定环电路在所述第一DLL之后输出的第二DLL值值和第一设定值，并将第一设定值更新为第二设定值。

10. 发明授权

US08432754B2 Memory control apparatus and mask timing adjusting method 有权
标题翻译：存储器控制装置和掩模定时调整方法
公开(公告)号：US08432754B2
公开(公告)日：2013-04-30
申请号：US13049695
申请日：2011-03-16
申请人： Keiichi Iwasaki
发明人： Keiichi Iwasaki
IPC分类号： G11C7/00
CPC分类号： G11C8/18 , G11C29/02 , G11C29/028 , G11C29/50012
摘要： A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.
摘要翻译：一种公开的同步存储器控制装置，用于与来自存储器电路的选通信号同步地从存储器电路读取的数据的接收包括使用掩码信号屏蔽选通信号的掩模电路; 定时测量电路延迟所述延迟选通信号中的每一个的延迟和锁存数据的多个单元中的选通信号; 以及产生掩模信号的掩模产生电路。定时测量电路在对应的屏蔽选通信号的第一个上升沿锁存每个延迟选通信号的数据。掩模生成电路包括具有多个延迟单位的延迟电路。屏蔽信号的开始定时与内部时钟同步地被调整，并且输出具有与延迟电路的所选择的延迟单位对应的延迟量的信号作为掩码信号。

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