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1. 发明申请

US20090231001A1 Signal recovery circuit 有权
标题翻译：信号恢复电路
公开(公告)号：US20090231001A1
公开(公告)日：2009-09-17
申请号：US12320409
申请日：2009-01-26
申请人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
发明人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H04L7/0331
摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual Phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
摘要翻译：提供了能够扩大接收余量的信号恢复电路。信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相互相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差，以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

2. 发明授权

US08311157B2 Signal recovery circuit 有权
标题翻译：信号恢复电路
公开(公告)号：US08311157B2
公开(公告)日：2012-11-13
申请号：US12320409
申请日：2009-01-26
申请人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
发明人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
IPC分类号： H04L27/00
CPC分类号： H03L7/08 , H04L7/0331
摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
摘要翻译：提供了能够扩大接收余量的信号恢复电路。信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差，以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

3. 发明授权

US08503595B2 Data judgment/phase comparison circuit 失效
标题翻译：数据判断/相位比较电路
公开(公告)号：US08503595B2
公开(公告)日：2013-08-06
申请号：US13255902
申请日：2009-09-29
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03K5/26
CPC分类号： H03K5/26 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/033
摘要： The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted. Depending on a relation among data outputs of total three symbols obtained by combining a symbol and symbols previous and subsequent thereto, it is selected that either the Early or the Late is to be outputted by a decision logic EL_LOGIC.
摘要翻译：本发明涉及一种包括时钟产生电路的时钟发生电路和信号再现电路，更具体地说，本发明提供一种能够通过单相时钟执行数据判断和相位比较两者的数据判断/相位比较电路并且提供包括数据判断/相位比较电路的CDR（时钟数据恢复）电路。相同的数据和时钟输入到具有正确判断数据所需的不同数据确定周期（建立/保持时间）的两个数据判断单元C_GOOD和C_BAD，并且具有较短的所需数据确定的数据判断单元C_GOOD的输出将周期作为数据判断/相位比较电路的数据输出。当两个数据判断单元的输出彼此不同时，输出表示时钟相位太早的信号Early，或指示时钟相位太迟的信号Late。根据通过组合符号和先前和之后的符号获得的总共三个符号的数据输出之间的关系，选择Early或Late由判决逻辑EL_LOGIC输出。

4. 发明授权

US08493103B2 Output driver circuit 有权
标题翻译：输出驱动电路
公开(公告)号：US08493103B2
公开(公告)日：2013-07-23
申请号：US12987092
申请日：2011-01-08
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K5/151 , H03K19/01721 , H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0286 , H04L25/03878
摘要： Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively. VSG_BK decides a voltage level at TXP, TXN, in the stationary state, keeping TXP, TXN as terminal nodes at impedance Z0, respectively.
摘要翻译：公开了除了传输速度的提高之外，还能够实现功率消耗的降低和/或传输波形质量的提高。输出驱动电路例如具有用于通过电压驱动正负输出节点（TXP，TXN）的电压信号生成电路块VSG_BK，用于产生脉冲信号的脉冲信号生成电路PGEN1，PGEN2 数据输入信号DIN_P，DIN_N和电流信号产生电路块ISG_BKp1，ISG_BKn1的转换，用于在脉冲信号的脉冲宽度的持续时间内通过电流驱动TXP，TXN。电流信号发生电路块分别对发生在阻抗Z0上的寄生电容器Cp1，Cp2进行充电，分别执行对TXP，TXN发生的寄生电容器Cp1，Cp2的高速充电。在固定状态下，VSG_BK决定TXP，TXN的电压电平，分别将TXP，TXN作为终端节点保持在阻抗Z0。

5. 发明申请

US20110001588A1 WAVEFORM EQUALIZATION CIRCUIT WITH PULSE WIDTH MODULATION 有权
标题翻译：波形宽度调制的波形均衡电路
公开(公告)号：US20110001588A1
公开(公告)日：2011-01-06
申请号：US12826648
申请日：2010-06-29
申请人： Fumio YUKI , Hiroki Yamashita , Koji Fukuda
发明人： Fumio YUKI , Hiroki Yamashita , Koji Fukuda
IPC分类号： H04B3/04
CPC分类号： H04B3/04
摘要： There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width. With the use of such a waveform equalization scheme as above, it is possible to attain reduction in power consumption due to simplification in circuit configuration, and further, use of CMOS circuits will enable power consumption to be held back to a low level.
摘要翻译：提供具有脉冲宽度调制的波形均衡电路，其包括脉冲宽度调整电平生成电路PWCLC1a，PWCLC2a，用于分别基于先前的输入数据单元Din_P，Din_N产生脉冲宽度调整电平VCNT，脉冲用于调整根据VCNT的脉冲宽度的宽度调整电路PWCC1a，PWCC2a以及用于整形来自每个脉冲宽度调节电路的输出信号的波形的波形整形电路WAC。脉冲宽度调整电路具有根据前述各输入数据单元的连续比特数进行控制的驱动功率，并且改变每个输出数据单元Do1_P，Do1_N的转换时间，从而调整脉冲宽度。通过使用如上所述的这种波形均衡方案，由于电路结构的简化，可以实现功耗的降低，此外，使用CMOS电路将能够将功耗抑制到低水平。

6. 发明授权

US07899144B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07899144B2
公开(公告)日：2011-03-01
申请号：US11937592
申请日：2007-11-09
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： The present invention is to provide a semiconductor integrated circuit device provided with a sufficient margin to variations of input waveforms. For example, the semiconductor integrated circuit device is provided with a clock and data determination circuit receiving an input data signal and a clock signal and outputting a recovered data signal, a first phase comparison signal and a second phase comparison signal and a clock signal generating circuit generating the clock signal with a phase corrected based on the first phase comparison signal and the second phase comparison signal. The clock and data determination circuit latches the input data signal in synchronization with the clock signal using a plurality of thresholds as determination reference and generates two kinds of candidates composed of combination of a recovered data signal and phase comparison signals by processing a latch result. Further, one of the two kinds of candidates is selected by a selector circuit based on a symbol of a recovered data signal at a previous cycle.
摘要翻译：本发明提供一种半导体集成电路器件，其对输入波形的变化提供足够的余量。例如，半导体集成电路装置具有时钟和数据判定电路，接收输入数据信号和时钟信号，并输出恢复的数据信号，第一相位比较信号和第二相位比较信号以及时钟信号发生电路利用基于第一相位比较信号和第二相位比较信号校正的相位产生时钟信号。时钟和数据确定电路使用多个阈值与时钟信号同步地锁存输入数据信号作为确定基准，并且通过处理锁存结果生成由恢复的数据信号和相位比较信号的组合组成的两种候选。此外，两种候选中的一种由选择器电路基于前一周期的恢复数据信号的符号来选择。

7. 发明授权

US07768330B2 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US07768330B2
公开(公告)日：2010-08-03
申请号：US12003443
申请日：2007-12-26
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
IPC分类号： H03K3/00
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.
摘要翻译：例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。

8. 发明申请

US20090207957A1 Clock recovery circuit 失效
标题翻译：时钟恢复电路
公开(公告)号：US20090207957A1
公开(公告)日：2009-08-20
申请号：US12320573
申请日：2009-01-29
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/081 , H03L7/0812 , H03L7/087 , H04L7/027 , H04L7/0276 , H04L7/10
摘要： A clock recovery circuit capable of simultaneously satisfying all of a bit synchronization period, a clock wander tracking performance, and a high high-frequency jitter tolerance. The clock recovery circuit includes: a phase difference detecting circuit that detects a phase difference between an input data signal and a recovery clock; an averaging circuit that averages the output of the phase difference detecting circuit; a sampling and holding circuit with resetting that samples and holds the output of the phase difference detecting circuit; and a recovery clock generating circuit that generates a recovery clock having a phase corresponding to the sum of the integral value of the output of the averaging circuit and the output of the sampling and holding circuit with resetting. The sampling and holding circuit with resetting receives a burst transmission start signal and samples and holds the output of the phase difference detecting. In addition, the sampling and holding circuit with resetting receives a burst transmission end signal and resets the held value to an initial value.
摘要翻译：一种时钟恢复电路，能够同时满足所有的位同步周期，时钟漂移跟踪性能和高高频抖动容限。时钟恢复电路包括：相位差检测电路，其检测输入数据信号和恢复时钟之间的相位差; 平均电路，对所述相位差检测电路的输出进行平均; 具有采样和保持相位差检测电路的输出的复位的采样和保持电路; 以及恢复时钟产生电路，其生成具有与平均电路的输出的积分值和采样保持电路的输出的复位相对应的相位的恢复时钟。具有复位的取样和保持电路接收脉冲串传输开始信号，采样并保持相位差检测的输出。此外，具有复位的采样和保持电路接收突发传输结束信号，并将保持值重置为初始值。

9. 发明申请

US20080204100A1 Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US20080204100A1
公开(公告)日：2008-08-28
申请号：US12003443
申请日：2007-12-26
申请人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
发明人： Fumio Yuuki , Hiroki Yamashita , Masayoshi Yagyu , Koji Fukuda
IPC分类号： H03K3/289 , H03K3/286
CPC分类号： H03K3/356191 , H03K3/356139 , H03K3/3562 , H03M9/00
摘要： For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.
摘要翻译：例如，在包括具有差分放大器配置的数据采集部分的逻辑电路中提供增益控制部分和公共节点控制部分，并且当点击信号为“H”电平时获取数据输入信号，并且锁存部分当点击信号为“L”电平时，锁存来自数据采集部分的数据输出信号。增益控制部分设置在差分放大器中的NMOS晶体管的公共节点之间，用于使高频带中差分放大器的增益高于低频带。当时钟信号为“L”电平时，公共节点控制部分用于控制电荷，以消除公共节点之间的电位差。因此，数据输出信号的转换时间被加速并且在锁存部分中增加了设置余量。因此，上述技术可以加速诸如锁存电路的各种逻辑电路的操作。

10. 发明申请

US20120249217A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20120249217A1
公开(公告)日：2012-10-04
申请号：US13500636
申请日：2010-10-04
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03K17/687 , H01L25/00 , H01L27/088 , H03K3/01
CPC分类号： H03K19/00384 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L27/088
摘要： A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
摘要翻译：通过调整偏移电压来实现高速半导体集成电路器件。例如，虚拟NMOS晶体管MND1（MND1a和MND1b）和MND2（MND2a和MND2b）分别连接到根据差分输入信号Din_p和Din_n操作的NMOS晶体管MN1和MN2的漏极输出。 MND1布置成与MN1相邻，并且MND1a的源极和MN1的漏极共享扩散层。 MND2被布置为与MN2相邻，并且MND2a的源极和MN2的漏极共享扩散层。 MND1和MND2用作用于抑制MN1和MN2的处理变化的虚拟晶体管，此外，它们还用作通过适当地向每个门施加偏移量设置信号OFST来调整偏移电压的装置，以提供一个到MN1或MN2的电容器。

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