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1. 发明授权

US08311157B2 Signal recovery circuit 有权
标题翻译：信号恢复电路
公开(公告)号：US08311157B2
公开(公告)日：2012-11-13
申请号：US12320409
申请日：2009-01-26
申请人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
发明人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
IPC分类号： H04L27/00
CPC分类号： H03L7/08 , H04L7/0331
摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
摘要翻译：提供了能够扩大接收余量的信号恢复电路。信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差，以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

2. 发明申请

US20090231001A1 Signal recovery circuit 有权
标题翻译：信号恢复电路
公开(公告)号：US20090231001A1
公开(公告)日：2009-09-17
申请号：US12320409
申请日：2009-01-26
申请人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
发明人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H04L7/0331
摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual Phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
摘要翻译：提供了能够扩大接收余量的信号恢复电路。信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相互相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差，以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

3. 发明申请

US20090224809A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR EVALUATING AN EYE-OPENING MARGIN 有权
标题翻译：半导体集成电路装置和评估眼睛开放标志的方法
公开(公告)号：US20090224809A1
公开(公告)日：2009-09-10
申请号：US12367067
申请日：2009-02-06
申请人： Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , kzuhisa Suzuki
发明人： Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , kzuhisa Suzuki
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H04L1/205 , H04L7/0008 , H04L7/0331 , H04L7/043
摘要： An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.
摘要翻译：一种用于高速串行数据接收电路的开眼边缘测量方法，其使用涉及在不固定时钟相位的情况下操作时钟数据恢复电路的眼睛开度边缘测量电路。在该方法中，也可以通过向相位信息给出偏移脉冲信号来添加抖动分量，来对接收到的数据进行误差加速度测试。该方法使用包括用于接收串行数据的串行器/解串行器电路（SerDes）和用于接收伴随时钟信号的参考串行器/解串行器电路（Ref_SerDes）的半导体集成电路器件。 SerDes电路通过恢复时钟将接收的串行数据转换成并行数据，恢复时钟的相位由Ref_SerDes电路生成的相位控制信号P_CS进行控制。来自脉冲形成电路的偏移脉冲信号Offset_Pulse被施加到相位控制信号P_CS以进行开眼余量测量。

4. 发明申请

US20120188013A1 RECEIVING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：接收电路，包括其的半导体器件和信息处理系统
公开(公告)号：US20120188013A1
公开(公告)日：2012-07-26
申请号：US13349236
申请日：2012-01-12
申请人： Yuji USHIO , Daisuke Hamano , Tatsunori Usugi
发明人： Yuji USHIO , Daisuke Hamano , Tatsunori Usugi
IPC分类号： H03F3/45
CPC分类号： H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： In a receiving circuit, and in a semiconductor device and an information processing system including the receiving circuit, the receiving circuit is configured to amplify a high-speed signal by a greater gain than a low-speed signal with a low electric power consumption. The receiving circuit includes a first amplifier and a second amplifier having a cutoff frequency lower than a cutoff frequency of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, an output from the second amplifier is subtracted from an output from the first amplifier, and a result is outputted from the receiving circuit.
摘要翻译：在接收电路中，并且在包括接收电路的半导体器件和信息处理系统中，接收电路被配置为以比具有低功耗的低速信号更大的增益来放大高速信号。接收电路包括第一放大器和具有低于第一放大器的截止频率的截止频率的第二放大器。接收信号被输入到第一放大器和第二放大器，从第一放大器的输出中减去来自第二放大器的输出，并且从接收电路输出结果。

5. 发明授权

US08443243B2 Semiconductor integrated circuit device and method for evaluating an eye-opening margin 有权
标题翻译：半导体集成电路装置及评估开眼余量的方法
公开(公告)号：US08443243B2
公开(公告)日：2013-05-14
申请号：US12367067
申请日：2009-02-06
申请人： Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , Kazuhisa Suzuki
发明人： Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , Kazuhisa Suzuki
IPC分类号： G06F11/00
CPC分类号： H03L7/08 , H04L1/205 , H04L7/0008 , H04L7/0331 , H04L7/043
摘要： An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.
摘要翻译：一种用于高速串行数据接收电路的开眼边缘测量方法，其使用涉及在不固定时钟相位的情况下操作时钟数据恢复电路的眼睛开度边缘测量电路。在该方法中，也可以通过向相位信息给出偏移脉冲信号来添加抖动分量，来对接收到的数据进行误差加速度测试。该方法使用包括用于接收串行数据的串行器/解串行器电路（SerDes）和用于接收伴随时钟信号的参考串行器/解串行器电路（Ref_SerDes）的半导体集成电路器件。 SerDes电路通过恢复时钟将接收的串行数据转换成并行数据，恢复时钟的相位由Ref_SerDes电路生成的相位控制信号P_CS进行控制。来自脉冲形成电路的偏移脉冲信号Offset_Pulse被施加到相位控制信号P_CS以进行开眼余量测量。

6. 发明申请

US20120187986A1 LATCH CIRCUIT, CDR CIRCUIT, AND RECEIVER 审中-公开
标题翻译：锁存电路，CDR电路和接收器
公开(公告)号：US20120187986A1
公开(公告)日：2012-07-26
申请号：US13349195
申请日：2012-01-12
申请人： Daisuke Hamano , Tatsunori Usugi
发明人： Daisuke Hamano , Tatsunori Usugi
IPC分类号： H03L7/06 , H03K3/356
CPC分类号： H03K3/356139 , H03L7/0807 , H04L7/033
摘要： A receiving circuit that consumes less electric power is provided. The present invention provides a latch circuit that latches a differential signal by interrupting an electric current generated by a differential input using a corresponding differential output when the differential signal is differentially amplified. By using the latch circuit, transmitted data can be received even if the voltage difference of the differential signal components of the received signal is small. As a result, the number of amplifiers can be reduced, thereby enabling the power consumption of the receiver to be reduced.
摘要翻译：提供消耗较少电力的接收电路。本发明提供了一种锁存电路，其通过在差分信号被差分放大时中断使用相应的差分输出的由差分输入产生的电流来锁存差分信号。通过使用锁存电路，即使接收信号的差分信号分量的电压差小，也可以接收发送数据。结果，可以减少放大器的数量，从而能够降低接收机的功耗。

7. 发明申请

US20120051480A1 PHASE LOCKED LOOP, CDR CIRCUIT, AND RECEIVING CIRCUIT 失效
标题翻译：相位锁定环，CDR电路和接收电路
公开(公告)号：US20120051480A1
公开(公告)日：2012-03-01
申请号：US13180620
申请日：2011-07-12
申请人： Tatsunori USUGI , Daisuke Hamano
发明人： Tatsunori USUGI , Daisuke Hamano
IPC分类号： H03D3/24 , H03L7/08
CPC分类号： H03L7/235 , H03L7/087
摘要： In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.
摘要翻译：在锁相环中，分别给予反馈时钟的至少一个周期的相位差的分频时钟分别被输入到与第一相位比较器和第二相位比较器进行相位比较，参考时钟。然后，通过接收信号和反馈时钟的相位比较的结果对第一和第二相位比较器的输出进行加权，并且使用加权输出对反馈时钟的相位调整进行相位调整。由此，能够降低基准时钟的频率，能够抑制功耗。

8. 发明授权

US08625730B2 Phase locked loop, CDR circuit, and receiving circuit 失效
标题翻译：锁相环，CDR电路和接收电路
公开(公告)号：US08625730B2
公开(公告)日：2014-01-07
申请号：US13180620
申请日：2011-07-12
申请人： Tatsunori Usugi , Daisuke Hamano
发明人： Tatsunori Usugi , Daisuke Hamano
IPC分类号： H03D3/24
CPC分类号： H03L7/235 , H03L7/087
摘要： In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.
摘要翻译：在锁相环中，分别给予反馈时钟的至少一个周期的相位差的分频时钟分别被输入到与第一相位比较器和第二相位比较器进行相位比较，参考时钟。然后，通过接收信号和反馈时钟的相位比较的结果对第一和第二相位比较器的输出进行加权，并且使用加权输出对反馈时钟的相位调整进行相位调整。由此，能够降低基准时钟的频率，能够抑制功耗。

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