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1. 发明授权

US08432186B1 Programmable logic switch 有权
标题翻译：可编程逻辑开关
公开(公告)号：US08432186B1
公开(公告)日：2013-04-30
申请号：US13484639
申请日：2012-05-31
申请人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto , Shinichi Yasuda , Masato Oda , Haruka Kusai , Kiwamu Sakuma
发明人： Koichiro Zaitsu , Kosuke Tatsumura , Mari Matsumoto , Shinichi Yasuda , Masato Oda , Haruka Kusai , Kiwamu Sakuma
IPC分类号： H03K19/173
CPC分类号： H03K19/018585 , G11C5/146 , G11C16/10 , G11C16/12 , H03K19/1737
摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.
摘要翻译：一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

2. 发明授权

US08829594B2 Nonvolatile programmable switches 有权
标题翻译：非易失性可编程开关
公开(公告)号：US08829594B2
公开(公告)日：2014-09-09
申请号：US13469867
申请日：2012-05-11
申请人： Kosuke Tatsumura , Kiwamu Sakuma , Koichiro Zaitsu , Mari Matsumoto
发明人： Kosuke Tatsumura , Kiwamu Sakuma , Koichiro Zaitsu , Mari Matsumoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0441 , H01L27/11568 , H01L29/66833
摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.
摘要翻译：根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值第二非易失性存储晶体管的电压降低。

3. 发明申请

US20130134499A1 NONVOLATILE PROGRAMMABLE SWITCHES 有权
标题翻译：非易失性可编程开关
公开(公告)号：US20130134499A1
公开(公告)日：2013-05-30
申请号：US13469867
申请日：2012-05-11
申请人： Kosuke TATSUMURA , Kiwamu Sakuma , Koichiro Zaitsu , Mari Matsumoto
发明人： Kosuke TATSUMURA , Kiwamu Sakuma , Koichiro Zaitsu , Mari Matsumoto
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0441 , H01L27/11568 , H01L29/66833
摘要： A nonvolatile programmable switch according to an embodiment includes: a first nonvolatile memory transistor including a first to third terminals connected to a first to third interconnects respectively; a second nonvolatile memory transistor including a fourth terminal connected to a fourth interconnect, a fifth terminal connected to the second interconnect, and a sixth terminal connected to the third interconnect, the first and second nonvolatile memory transistors having the same conductivity type; and a pass transistor having a gate electrode connected to the second interconnect. When the first and fourth interconnects are connected to a first power supply while the third interconnect is connected to a second power supply having a higher voltage than that of the first power supply, a threshold voltage of the first nonvolatile memory transistor increases, and a threshold voltage of the second nonvolatile memory transistor decreases.
摘要翻译：根据实施例的非易失性可编程开关包括：第一非易失性存储晶体管，包括分别连接到第一至第三互连的第一至第三端子; 第二非易失性存储晶体管，包括连接到第四互连的第四端子，连接到第二互连的第五端子和连接到第三互连件的第六端子，具有相同导电类型的第一和第二非易失性存储器晶体管; 以及具有连接到第二互连的栅电极的传输晶体管。当第一和第四互连连接到第一电源，而第三互连连接到具有比第一电源的电压更高的电压的第二电源时，第一非易失性存储晶体管的阈值电压增加，阈值第二非易失性存储晶体管的电压降低。

4. 发明申请

US20130175490A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130175490A1
公开(公告)日：2013-07-11
申请号：US13547645
申请日：2012-07-12
申请人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka KUSAI , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/088 , H01L27/24 , H01L21/3205 , H01L21/768 , H01L21/265 , H01L21/02
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

5. 发明授权

US09087715B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09087715B2
公开(公告)日：2015-07-21
申请号：US13547645
申请日：2012-07-12
申请人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
发明人： Haruka Kusai , Kiwamu Sakuma , Shosuke Fujii , Masumi Saitoh , Masahiro Kiyotoshi
IPC分类号： H01L27/115 , H01L27/088 , H01L21/265 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L27/24 , G11C16/04 , H01L29/66 , H01L29/68 , H01L29/788 , H01L29/792 , G11C16/10 , H01L29/82
CPC分类号： H01L27/088 , G11C16/04 , G11C16/10 , H01L21/02367 , H01L21/265 , H01L21/32051 , H01L21/76877 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/685 , H01L29/788 , H01L29/792 , H01L29/82
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括具有存储单元的鳍式堆叠层结构和连接到该结构的端部的光束。结构和梁中的每一个包括沿垂直方向堆叠的半导体层。梁包括设置在梁的一端的接触部分和设置在接触部分和结构的端部之间的低电阻部分。

6. 发明授权

US09076722B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09076722B2
公开(公告)日：2015-07-07
申请号：US13547567
申请日：2012-07-12
申请人： Kiwamu Sakuma , Masahiro Kiyotoshi , Atsuhiro Kinoshita , Haruka Kusai
发明人： Kiwamu Sakuma , Masahiro Kiyotoshi , Atsuhiro Kinoshita , Haruka Kusai
IPC分类号： H01L29/76 , H01L29/788 , H01L29/66 , H01L29/792 , H01L27/24 , H01L21/8234 , H01L27/115 , H01L27/22 , H01L21/84 , H01L27/12 , H01L27/06
CPC分类号： H01L45/1233 , H01L21/823431 , H01L21/845 , H01L27/0688 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/1211 , H01L27/222 , H01L27/2454 , H01L27/2481 , H01L29/7881 , H01L29/792 , H01L45/1206 , H01L45/1253
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括鳍式堆叠层结构。每个结构包括沿垂直方向堆叠的半导体层。辅助栅电极沿面内方向设置，并在结构垂直方向的一个表面上划分。

7. 发明授权

US08710580B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08710580B2
公开(公告)日：2014-04-29
申请号：US13689026
申请日：2012-11-29
申请人： Kiwamu Sakuma , Haruka Kusai , Shosuke Fujii , Li Zhang , Masahiro Kiyotoshi , Masao Shingu
发明人： Kiwamu Sakuma , Haruka Kusai , Shosuke Fujii , Li Zhang , Masahiro Kiyotoshi , Masao Shingu
IPC分类号： H01L45/00 , H01L27/115 , H01L21/265
CPC分类号： H01L27/1157 , H01L21/265 , H01L21/845 , H01L27/11551 , H01L27/11578 , H01L27/1211 , H01L27/2436 , H01L27/2481 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L45/04
摘要： According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.
摘要翻译：根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

8. 发明授权

US08710485B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08710485B2
公开(公告)日：2014-04-29
申请号：US13458042
申请日：2012-04-27
申请人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
发明人： Masumi Saitoh , Toshinori Numata , Kiwamu Sakuma , Haruka Kusai , Takayuki Ishikawa
IPC分类号： H01L29/06 , H01L47/00
CPC分类号： H01L21/823431 , H01L27/101 , H01L27/1211 , H01L27/2409 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.
摘要翻译：根据一个实施例，半导体器件包括具有第一至第三半导体层的鳍式堆叠层结构以及选择第一至第三半导体层之一的第一至第三层选择晶体管。第二层选择晶体管通常在第二半导体层中导通，并且在第一和第三半导体层中被控制为导通或截止。被第二层选择晶体管的栅电极覆盖的第二半导体层的沟道区域具有金属硅化物。

9. 发明申请

US20120280303A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20120280303A1
公开(公告)日：2012-11-08
申请号：US13366845
申请日：2012-02-06
申请人： Masahiro KIYOTOSHI , Kiwamu Sakuma , Haruka Kusai
发明人： Masahiro KIYOTOSHI , Kiwamu Sakuma , Haruka Kusai
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11556 , H01L27/11524 , H01L29/7889
摘要： According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films.
摘要翻译：根据一个实施例，沿着第一方向延伸的第一沟槽以堆叠结构形成，其中多个隔离膜和多个沟道半导体膜交替堆叠。通过在沟道半导体膜中形成来自第一沟槽的凹部来形成第一空间。在第一空间中形成隧道电介质膜，并且第一空间进一步填充浮栅电极膜。形成在第一方向上以预定间隔划分堆叠结构的第二沟槽，以便在第一方向上彼此相邻的存储单元之间划分浮栅电极膜，但不划分沟道半导体膜。

10. 发明申请

US20130069134A1 MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
标题翻译：包含两个浮动门结构的晶体管的存储器
公开(公告)号：US20130069134A1
公开(公告)日：2013-03-21
申请号：US13608436
申请日：2012-09-10
申请人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
发明人： Tetsufumi TANAMOTO , Kosuke Tatsumura , Kiwamu Sakuma , Atsuhiro Kinoshita , Shinobu Fujita , Koichi Muraoka
IPC分类号： H01L27/11
CPC分类号： H01L29/42332 , G11C11/412 , G11C14/0063 , H01L27/1104 , H01L29/7881
摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
摘要翻译：在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极，第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜，第四浮栅，第六绝缘膜和第二控制栅极。

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