专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5892291A Registration accuracy measurement mark 失效
标题翻译：注册精度测量标记
公开(公告)号：US5892291A
公开(公告)日：1999-04-06
申请号：US670313
申请日：1996-06-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02 , H01L23/544
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

2. 发明授权

US06323560B1 Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US06323560B1
公开(公告)日：2001-11-27
申请号：US09492750
申请日：2000-01-27
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： H01L2358
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

3. 发明授权

US6068952A Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photomask and method of exposure thereof 有权
标题翻译：注册精度测量标记，修理标记缺陷的方法，具有标记的光掩模，制造光掩模的方法及其曝光方法
公开(公告)号：US6068952A
公开(公告)日：2000-05-30
申请号：US231664
申请日：1999-01-15
申请人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
发明人： Koichiro Narimatsu , Shigenori Yamashita , Nobuyuki Yoshioka , Shinya Soeda , Atsushi Hachisuka , Koji Taniguchi , Yuki Miyamoto , Takayuki Saito , Ayumi Minamide
IPC分类号： G03F1/36 , G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027 , H05K1/02
CPC分类号： G03F7/706 , G03F7/70633 , Y10T428/24802 , Y10T428/24917
摘要： The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.
摘要翻译：本发明包括形成在第一层中的第一半导体元件形成元件，通过与第一半导体元件形成元件相同的制造步骤形成的第一测量标记，形成在第一层之上的第二层中的第二半导体元件形成元件，以及在与第二半导体元件形成部件相同的制造步骤中形成的用于测量第一和第二半导体元件形成部件之间的配准精度的第二测量标记。第一测量标记具有在照射光时受到与第一半导体元件形成部件相同的像差影响的图案，并且第二测量标记具有受光照射时受到与第二半导体元件形成部件相同的像差影响的图案。因此，可以提供考虑到像差影响的配准精度测量标记。

4. 发明授权

US06388295B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06388295B1
公开(公告)日：2002-05-14
申请号：US09663717
申请日：2000-09-18
申请人： Tomohiro Yamashita , Yoshinori Okumura , Atsushi Hachisuka , Shinya Soeda
发明人： Tomohiro Yamashita , Yoshinori Okumura , Atsushi Hachisuka , Shinya Soeda
IPC分类号： H01L2976
CPC分类号： H01L21/823493 , H01L21/761 , H01L27/10897
摘要： The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.
摘要翻译：半导体器件具有三重阱结构。三井等井在深度方向具有杂质浓度分布，根据所需的功能确定。因此，即使在小型化结构中也能够实现抑制漏电流等所需的性能。

5. 发明授权

US06218235B1 Method of manufacturing a DRAM and logic device 失效
标题翻译：制造DRAM和逻辑器件的方法
公开(公告)号：US06218235B1
公开(公告)日：2001-04-17
申请号：US09542876
申请日：2000-04-04
申请人： Atsushi Hachisuka , Hiroyasu Nohsoh , Shinya Soeda
发明人： Atsushi Hachisuka , Hiroyasu Nohsoh , Shinya Soeda
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10894
摘要： A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.
摘要翻译：在不降低半导体器件的可靠性并使制造工艺不必要地复杂的情况下，提供具有在同一半导体衬底上的存储器件和逻辑器件的半导体器件的制造方法。在逻辑器件形成区域中用作硅化物保护膜的氧化硅膜经受湿均匀蚀刻。该过程完全去除存储器件形成区域中的氧化硅膜。因此，氧化硅膜仅留在逻辑器件形成区域中的规定部分。结果，氧化硅膜不留在由栅电极之间的氮化硅膜形成的凹部的内壁上。因此，存储器件形成区域中的源极/漏极区域形成良好的自对准接触开口。

6. 发明授权

US06331462B1 Manufacturing method of a semiconductor device for desired circuit patterns 失效
标题翻译：用于所需电路图案的半导体器件的制造方法
公开(公告)号：US06331462B1
公开(公告)日：2001-12-18
申请号：US09453807
申请日：1999-12-03
申请人： Tatsuo Kasaoka , Atsushi Hachisuka , Shinya Soeda
发明人： Tatsuo Kasaoka , Atsushi Hachisuka , Shinya Soeda
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10873
摘要： A semiconductor substrate is arranged to have a DRAM area in which to form at a high density gate electrodes of transistors serving as DRAM components, and a peripheral circuit area in which to form at a relatively low density gate electrodes of transistors as peripheral circuit components. A resist film is formed in corresponding relation to the gate electrodes of the DRAM. After an insulating film is etched, a resist film is formed in corresponding relation to the gate electrodes of the peripheral circuits. A conductive layer is then etched while the resist film and insulating film left in the DRAM area are being used as masks, whereby the gate electrodes are formed in the DRAM area and peripheral circuit area.
摘要翻译：半导体衬底被布置成具有在作为DRAM部件的晶体管的高密度栅电极形成的DRAM区域，以及在相对低密度的晶体管的栅极形成外围电路部件的外围电路区域。以与DRAM的栅电极对应的关系形成抗蚀剂膜。在蚀刻绝缘膜之后，以与外围电路的栅电极对应的关系形成抗蚀剂膜。然后蚀刻导电层，同时将残留在DRAM区域中的抗蚀剂膜和绝缘膜用作掩模，由此在DRAM区域和外围电路区域中形成栅电极。

7. 发明授权

US06765251B2 Semiconductor device having interconnection structure 失效
标题翻译：具有互连结构的半导体器件
公开(公告)号：US06765251B2
公开(公告)日：2004-07-20
申请号：US09227935
申请日：1999-01-11
申请人： Eiji Hasunuma , Hideki Genjo , Shigeru Shiratake , Atsushi Hachisuka , Koji Taniguchi
发明人： Eiji Hasunuma , Hideki Genjo , Shigeru Shiratake , Atsushi Hachisuka , Koji Taniguchi
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L21/28568 , H01L21/76814 , H01L21/76831 , H01L27/10808
摘要： In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.
摘要翻译：在半导体装置中，为了满足半导体装置的小型化使接触孔的直径减小的要求，没有被氢氟酸腐蚀的抗HF侧壁膜由隔离膜形成，例如氮化物膜设置在接触孔的侧壁上。此外，在接触孔下端附近的硅衬底1中设置有连接到一对n型源极/漏极区域中的一个和到达p型隔离区域的第一杂质区域的第二杂质区域。由于这种结构，可以根据小型半导体器件的需要防止用于形成互连层的直径的膨胀，因此可以提供稳定半导体器件的操作特性的半导体器件及其制造方法。

8. 发明授权

US6163062A Semiconductor device having a metallic fuse member and cutting method thereof with laser light 失效
标题翻译：具有金属熔断元件的半导体器件及其激光切割方法
公开(公告)号：US6163062A
公开(公告)日：2000-12-19
申请号：US71158
申请日：1998-05-04
申请人： Shigeru Shiratake , Hideki Genjo , Yasuhiro Ido , Atsushi Hachisuka , Koji Taniguchi
发明人： Shigeru Shiratake , Hideki Genjo , Yasuhiro Ido , Atsushi Hachisuka , Koji Taniguchi
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L21/76888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a plurality of fuse members (1a, 1b) composed of a metal that can be cut by laser light (4), disposed over a semiconductor substrate (5). The length L of the fuse members (1a, 1b) is smaller than a value obtained by subtracting an alignment error .alpha. of the laser light (4) from a spot diameter D of the laser light (4), i.e., the value (D-.alpha.). The fuse members (1a, 1b) are spaced a distance l larger than a value obtained by adding the alignment error .alpha. to the half of the spot diameter D, i.e., the value (D/2+.alpha.).
摘要翻译：一种半导体器件具有多个由可由激光（4）切割的金属构成的保险丝构件（1a，1b），设置在半导体衬底（5）上。保险丝构件（1a，1b）的长度L小于从激光（4）的光斑直径D减去激光（4）的取向误差α所得到的值，即值（D - α ）。保险丝构件（1a，1b）的间隔距离l大于通过将对准误差α加到光斑直径D的一半，即值（D / 2 +α）而获得的值。

9. 发明授权

US06784066B2 Method for manufacturing semiconductor device and semiconductor device manufactured thereby 失效
标题翻译：由此制造半导体器件和半导体器件的方法
公开(公告)号：US06784066B2
公开(公告)日：2004-08-31
申请号：US09960974
申请日：2001-09-25
申请人： Atsushi Hachisuka
发明人： Atsushi Hachisuka
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/76834 , H01L21/76897 , H01L21/823468 , H01L27/10873 , H01L29/6656
摘要： A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.
摘要翻译：在具有DRAM区域和逻辑区域的半导体衬底上形成多个栅电极。接下来，分别在栅电极的侧面分别形成各自包括覆盖栅电极的侧面的氮化硅膜和覆盖氮化硅膜的氧化硅膜的侧壁。在逻辑区域中形成具有LDD结构的晶体管之后，通过湿蚀刻去除形成在栅电极侧面上的氧化硅膜。接下来，在半导体衬底的整个表面上形成氮化硅膜，并在氮化硅膜上形成层间电介质。

10. 发明授权

US5672533A Field effect transistor having impurity regions of different depths and manufacturing method thereof 失效
标题翻译：具有不同深度的杂质区域的场效应晶体管及其制造方法
公开(公告)号：US5672533A
公开(公告)日：1997-09-30
申请号：US555414
申请日：1995-11-09
申请人： Hideaki Arima , Makoto Ohi , Natsuo Ajika , Atsushi Hachisuka , Tomonori Okudaira
发明人： Hideaki Arima , Makoto Ohi , Natsuo Ajika , Atsushi Hachisuka , Tomonori Okudaira
IPC分类号： H01L21/8242 , H01L29/68 , H01L29/76 , H01L29/78 , H01L29/92 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L27/1085 , H01L27/10891 , H01L27/10894 , H01L29/66659
摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
摘要翻译：公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区，电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式