专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5781062A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5781062A
公开(公告)日：1998-07-14
申请号：US582416
申请日：1996-01-03
申请人： Koichiro Mashiko , Kimio Ueda , Hiroaki Suzuki , Hiroyuki Morinaka
发明人： Koichiro Mashiko , Kimio Ueda , Hiroaki Suzuki , Hiroyuki Morinaka
IPC分类号： G11C5/14 , G11C11/407 , H03K19/00 , H03K19/0948 , G05F1/10
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).
摘要翻译：逻辑电路（Li）通过PMOS晶体管（Q1）连接到与实际电源（VDD）连接的虚拟电源线（VDDV）和连接到实际地线（GND）的虚拟接地线（GNDV）之间通过一个NMOS晶体管（Q2）。在激活期间，晶体管（Q1，Q2）恒定导通，虚拟电源线（VDDV）和虚拟接地线（GNDV）分别处于电源电位（VDD）和接地电位（GND）。在待机期间，晶体管（Q1，Q2）周期性地重复导通/非导通，对虚拟电源线（VDDV）和虚拟接地线（GNDV）进行充电和放电，从而抑制功耗，同时防止由逻辑电路（Li）。

2. 发明授权

US06242786B1 SOI Semiconductor device with field shield electrode 失效
标题翻译：具有场屏蔽电极的SOI半导体器件
公开(公告)号：US06242786B1
公开(公告)日：2001-06-05
申请号：US09213280
申请日：1998-12-17
申请人： Yoshiki Wada , Hirotada Kuriyama , Kimio Ueda , Koichiro Mashiko , Hiroaki Suzuki
发明人： Yoshiki Wada , Hirotada Kuriyama , Kimio Ueda , Koichiro Mashiko , Hiroaki Suzuki
IPC分类号： H01L2940
CPC分类号： H01L21/76264 , H01L21/76291 , H01L27/1203
摘要： A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.
摘要翻译：形成由一种晶体管组成的场屏蔽部分，以将存储器单元的NMOS区域与其他区域电绝缘。场屏蔽部分包括场屏蔽栅极电极层，p型区域和栅极绝缘膜。该晶体管的阈值被设定为高于电源电压，并且其栅极电极层处于浮置状态。不需要在场屏蔽栅电极层设置用于施加规定电压的接触部。因此，可以减小在场屏蔽栅电极层中形成接触部分的区域。结果，提供了一种其布局面积减小的半导体器件。

3. 发明授权

US5541529A Field programmable gate array transferring signals at high speed 失效
标题翻译：现场可编程门阵列以高速传输信号
公开(公告)号：US5541529A
公开(公告)日：1996-07-30
申请号：US450757
申请日：1995-05-25
申请人： Koichiro Mashiko , Hiroaki Suzuki
发明人： Koichiro Mashiko , Hiroaki Suzuki
IPC分类号： G11C11/413 , H03K19/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17792 , H03K19/0013 , H03K19/1736 , H03K19/17704
摘要： A field programmable gate array includes a logic blocks, switching elements for establishing a signal propagation path, and memory cells provided corresponding to the switching elements for storing data determining on and off states of corresponding switching elements. In this gate array, a supply voltage fed to a power input terminal is transmitted to power supply nodes of logic circuit blocks. A booster circuit boosts the supply voltage fed to the power input terminal and feeds the boosted voltage to power supply nodes of memory cells for programming a signal propagation path. A high-level signal potential of each memory cell is fed to the gate of an n-channel MOS transistor which functions as the switching element. The switching elements are disposed on signal lines and serve to interconnect the signal lines selectively to establish a signal propagation path. The current supply capability of the MOS transistors is enhanced to realize faster propagation of the signal, and any harmful influence of the threshold voltage exerted on the signal amplitude loss can be suppressed by a rise of the gate potential in each MOS transistor.
摘要翻译：现场可编程门阵列包括逻辑块，用于建立信号传播路径的开关元件，以及与开关元件对应地提供的存储单元，用于存储确定相应开关元件的导通和截止状态的数据。在该门阵列中，馈送到电力输入端的电源电压被发送到逻辑电路块的电源节点。升压电路提高馈送到电源输入端的电源电压，并将升压的电压馈送到存储器单元的电源节点，以编程信号传播路径。每个存储单元的高电平信号电位被馈送到用作开关元件的n沟道MOS晶体管的栅极。开关元件设置在信号线上并用于选择性地互连信号线以建立信号传播路径。提高MOS晶体管的电流供应能力以实现信号的更快的传播，并且通过每个MOS晶体管中的栅极电位的上升可以抑制施加在信号幅度损失上的阈值电压的任何有害影响。

4. 发明授权

US5397937A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5397937A
公开(公告)日：1995-03-14
申请号：US70249
申请日：1993-06-02
申请人： Kimio Ueda , Hiroaki Suzuki
发明人： Kimio Ueda , Hiroaki Suzuki
IPC分类号： H01L21/8249 , H01L27/06 , H03K17/04 , H03K17/567 , H03K17/62 , H03K19/08 , H03K19/21 , H03K19/02
CPC分类号： H03K19/21 , H03K17/6257
摘要： There is disclosed a semiconductor integrated circuit comprising pass transistor circuits (PT3, PT4) for producing logically complementary signals. The output of the pass transistor circuit (PT3) is connected to the base electrode of an NPN bipolar transistor (BN1), and the output of the pass transistor circuit (PT4) is connected to the gate electrode of an NMOS transistor (MN9). PMOS transistors (MP15, MP16) are connected between the outputs of the pass transistor circuits (PT3, PT4) and a first potential (VDD). The gate electrodes of the PMOS transistors (MP15, MP16) are connected to the outputs of the pass transistor circuits (PT3, PT4). The bipolar transistor (BN1) having a large driving force charges and discharges a load capacity (CL1) connected to an output terminal in response to the output signal of the pass transistor circuit (PT3). This provides for a logic circuit which operates at high speeds in the semiconductor integrated circuit.
摘要翻译：公开了一种半导体集成电路，包括用于产生逻辑互补信号的传输晶体管电路（PT3，PT4）。传输晶体管电路（PT3）的输出端连接到NPN双极晶体管（BN1）的基极，传输晶体管电路（PT4）的输出端连接到NMOS晶体管（MN9）的栅电极。 PMOS晶体管（MP15，MP16）连接在传输晶体管电路（PT3，PT4）的输出端和第一电位（VDD）之间。 PMOS晶体管（MP15，MP16）的栅电极连接到传输晶体管电路（PT3，PT4）的输出端。具有大驱动力的双极型晶体管（BN1）响应于传输晶体管电路（PT3）的输出信号，对连接到输出端子的负载电容（CL1）进行充电和放电。这提供了在半导体集成电路中以高速工作的逻辑电路。

5. 发明授权

US09606494B2 Printing control device and printing control system that generate toner-scattering prevention plane data 有权
公开(公告)号：US09606494B2
公开(公告)日：2017-03-28
申请号：US14483745
申请日：2014-09-11
申请人： Yuji Kogusuri , Takanori Itoh , Yuichi Habu , Hiroaki Suzuki
发明人： Yuji Kogusuri , Takanori Itoh , Yuichi Habu , Hiroaki Suzuki
IPC分类号： G03G15/08 , G03G15/00
CPC分类号： G03G15/6585 , G03G2215/0129
摘要： A printing control device includes a toner-scattering prevention plane generating unit that generates toner-scattering prevention plane data indicating that clear toner is applied to an outline drawing that is identified from target data for print; and an image-data generating unit that generates image data that includes the outline drawing by using the toner-scattering prevention plane data.

6. 发明授权

US09385389B2 Fuel cell 有权
标题翻译：燃料电池
公开(公告)号：US09385389B2
公开(公告)日：2016-07-05
申请号：US14112753
申请日：2012-05-16
申请人： Goro Fujita , Hiroaki Suzuki
发明人： Goro Fujita , Hiroaki Suzuki
IPC分类号： H01M8/10
CPC分类号： H01M8/1065 , H01M8/1067 , Y02E60/521
摘要： An electrolyte membrane 22 constituting a membrane electrode assembly includes thick portions 23 having a relatively large thickness. The thick portions 23 have a strip shape and are disposed at a predetermined distance from each other along the electric conduction direction. The thick portions 23 extend from one side L1 of the electrolyte membrane 22 extending in a direction perpendicular to the electric conduction direction to the other side L2 of the electrolyte membrane 22 extending in the direction perpendicular to the electric conduction direction. The thick portions 23 have a convex shape with respect to the anode side surface and the cathode side surface of the electrolyte membrane 22.
摘要翻译：构成膜电极组件的电解质膜22包括厚度较大的厚壁部23。厚壁部23为带状，沿着导电方向彼此隔开规定距离。厚部23从与导电方向垂直的方向延伸的电解质膜22的一侧L1延伸到与导电方向垂直的方向延伸的电解质膜22的另一侧L2。厚壁部23相对于电解质膜22的阳极侧面和阴极侧面呈凸形。

7. 发明授权

US09344604B2 Display processing apparatus correcting color saturation due to gloss, image forming system, and computer program product 有权
标题翻译：显示处理装置校正由于光泽，图像形成系统和计算机程序产品引起的色彩饱和度
公开(公告)号：US09344604B2
公开(公告)日：2016-05-17
申请号：US13610572
申请日：2012-09-11
申请人： Ryonosuke Miyazaki , Hiroaki Suzuki
发明人： Ryonosuke Miyazaki , Hiroaki Suzuki
IPC分类号： H04N1/54 , H04N1/60
CPC分类号： H04N1/54 , H04N1/6011
摘要： A display processing apparatus includes a first correcting unit that, based on original data containing first-type color image data that indicates a color image in each drawing area and containing first-type gloss control image data that indicates a type of gloss effect to be given to a recording medium and indicates a gloss area to which the gloss effect is to be given in each drawing area, corrects color saturation of an area in the first-type color image data that corresponds to the gloss area specified by the first-type gloss control image data depending on the type of gloss effect, to thereby generate first-type corrected image data; and a display control unit that, on a display unit, displays the first-type corrected image data as a print preview of a projected printing result of the original data.
摘要翻译：显示处理装置包括：第一校正单元，其基于包含指示每个绘图区域中的彩色图像的第一类型彩色图像数据的原始数据，并且包含指示要给出的光泽效果的类型的第一类型光泽控制图像数据并且指示在每个绘图区域中给予光泽效果的光泽区域，校正与由第一类型光泽指定的光泽区域相对应的第一类型彩色图像数据中的区域的颜色饱和度根据光泽效果的类型控制图像数据，从而生成第一类型校正图像数据; 以及显示控制单元，其在显示单元上显示所述第一类型校正图像数据作为所述原始数据的投影打印结果的打印预览。

8. 发明授权

US09291979B2 Device, system, method, and recording medium having computer program for controlling printing 有权
标题翻译：具有用于控制打印的计算机程序的装置，系统，方法和记录介质
公开(公告)号：US09291979B2
公开(公告)日：2016-03-22
申请号：US14578871
申请日：2014-12-22
申请人： Makoto Yoshida , Hiroaki Suzuki
发明人： Makoto Yoshida , Hiroaki Suzuki
IPC分类号： G03G15/00 , G03G15/01
CPC分类号： G03G15/6585 , G03G15/0105 , G03G15/657
摘要： A printing control device includes a glossiness target value determining unit that determines a glossiness target value indicating a target of glossiness of image data as a print target, a color separation amount determining unit that determines color separation amounts of a plurality of colored color materials as amounts of the colored color materials to be allocated to the respective colored color materials based on a sum of respective amounts of the colored color materials for the glossiness target value, a color separation processing unit that executes color replacement among a plurality of pieces of colored plane data based on the color separation amounts of the respective colored color materials, and an image data generator that generates the image data based on the pieces of colored plane data on which the color replacement has been executed.
摘要翻译：打印控制装置包括：光泽度目标值确定单元，其确定指示作为打印对象的图像数据的光泽度的目标的光泽度目标值;颜色分离量确定单元，其将多个着色色素的颜色分离量确定为量基于用于光泽度目标值的彩色着色材料的相应量的总和，分配给各个着色色材料的着色色材料的色分离处理单元在多条彩色平面数据之间执行颜色替换基于各色着色材料的颜色分离量，以及基于执行了颜色替换的彩色平面数据生成图像数据的图像数据生成器。

9. 发明授权

US09177233B2 Display processing apparatus, image forming system, and computer-readable storage medium 有权
标题翻译：显示处理装置，图像形成系统和计算机可读存储介质
公开(公告)号：US09177233B2
公开(公告)日：2015-11-03
申请号：US14339604
申请日：2014-07-24
申请人： Ryonosuke Miyazaki , Tomoyoshi Takeuchi , Yasushi Yamaguchi , Hiroaki Suzuki
发明人： Ryonosuke Miyazaki , Tomoyoshi Takeuchi , Yasushi Yamaguchi , Hiroaki Suzuki
IPC分类号： H04N1/40 , G06K15/02 , G03G15/00 , G06F3/12
CPC分类号： G06K15/1889 , G03G15/502 , G03G15/6585 , G03G2215/00805 , G06F3/1208 , G06K15/1886
摘要： A display processing apparatus includes a receiving unit configured to receive display information indicating whether gloss-control plane image data is displayed and whether clear plane image data is displayed. The gloss-control plane image data specifies a type of a surface effect applied to a recording medium and a glossy area to which the surface effect is to be applied, and indicates a color of the glossy area when being displayed. The clear plane image data specifies a transparent image formed on the recording medium and indicates a color of the transparent image when being displayed. The apparatus also includes a generating unit configured to synthesize color plane image data indicating a color image and one of the gloss-control plane image data and the clear plane image data that is specified to be displayed thus to generate a synthetic image.
摘要翻译：显示处理装置包括接收单元，被配置为接收指示是否显示光泽度控制平面图像数据的显示信息以及是否显示清晰平面图像数据。光泽度控制平面图像数据指定施加到记录介质的表面效果的类型和要施加表面效果的光泽区域，并且在显示时指示光泽区域的颜色。透明平面图像数据指定形成在记录介质上的透明图像，并且在显示时指示透明图像的颜色。该装置还包括：生成单元，被配置为合成指示彩色图像的彩色平面图像数据和指定为显示的光泽度控制平面图像数据和清晰平面图像数据之一，以生成合成图像。

10. 发明授权

US08934827B2 Print control apparatus, printing system, and print control method 有权
标题翻译：打印控制装置，打印系统和打印控制方法
公开(公告)号：US08934827B2
公开(公告)日：2015-01-13
申请号：US13422840
申请日：2012-03-16
申请人： Takashi Yoshikawa , Hiroaki Suzuki , Hiroo Kitagawa
发明人： Takashi Yoshikawa , Hiroaki Suzuki , Hiroo Kitagawa
IPC分类号： G03G15/20 , G03G15/00
CPC分类号： G03G15/6585 , G03G15/50
摘要： A print control apparatus includes a generating unit that generates clear-toner plane data based on gloss-control plane data, which contains a gloss control value for specifying a type of a surface effect being a visual or a tactile effect applied to the recording medium and for specifying a region to which the surface effect is applied in the recording medium, and clear plane data, which contains a density value for specifying a transparent image other than the surface effect; and an outputting unit that outputs the clear-toner plane data. When a region where the gloss control value is specified in the gloss-control plane data and a region where the density value is specified in the clear plane data overlap each other, the generating unit sets a value of the clear-toner plane data to the gloss control value or the density value, based on a predetermined condition.
摘要翻译：打印控制装置包括生成单元，该生成单元基于光泽控制面数据生成清晰调色剂平面数据，该数据包含用于指定作为施加到记录介质的视觉效果或触觉效果的表面效果的类型的光泽度控制值，以及用于指定在记录介质中施加表面效应的区域，以及清除平面数据，其包含用于指定除了表面效果之外的透明图像的浓度值; 以及输出单元，其输出清色调色剂平面数据。当在光泽控制平面数据中指定光泽度控制值的区域和在清晰平面数据中指定浓度值的区域彼此重叠时，生成单元将透明调色剂平面数据的值设置为光泽度控制值或密度值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式