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1. 发明授权

US09564965B2 Signal monitoring apparatus, signal transmitting/receiving apparatus, and communication apparatus 有权
标题翻译：信号监视装置，信号发送/接收装置和通信装置
公开(公告)号：US09564965B2
公开(公告)日：2017-02-07
申请号：US14420146
申请日：2012-08-22
申请人： Yoshiki Wada
发明人： Yoshiki Wada
IPC分类号： H04B10/40 , H04B10/079
CPC分类号： H04B10/0795 , H04B10/40
摘要： A signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device includes: a difference value calculator that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.
摘要翻译：信号监视装置，信号发送/接收装置和通信装置，其实现了诊断结果和信号值的容易获取，并进一步实现诊断结果的快速获取。信号监视装置包括：差分值计算器，对于待监视的信号，时间顺序地计算其信号值和预先设定的阈值之间的差值; 以及存储器，其根据预先设定的规则更新并存储按时间顺序计算的差值。

2. 发明申请

US20150222353A1 SIGNAL MONITORING APPARATUS, SIGNAL TRANSMITTING/RECEIVING APPARATUS, AND COMMUNICATION APPARATUS 有权
标题翻译：信号监控装置，信号发送/接收装置和通信装置
公开(公告)号：US20150222353A1
公开(公告)日：2015-08-06
申请号：US14420146
申请日：2012-08-22
申请人： Yoshiki Wada
发明人： Yoshiki Wada
IPC分类号： H04B10/079 , H04B10/40
CPC分类号： H04B10/0795 , H04B10/40
摘要： An object of the present invention is to provide a signal monitoring device, a signal transmission/reception device and a communication device, which realize easy acquisition of a diagnosis result and a signal value, and further realize fast acquisition of the diagnosis result. A signal monitoring device (30) according to the present invention includes: a difference value calculator (12) that time-sequentially calculates, for a signal to be monitored, a difference value between a signal value thereof and a previously set threshold; and a storage (13) that updates and stores the time-sequentially calculated difference value in accordance with a previously set rule.
摘要翻译：本发明的目的是提供一种信号监视装置，信号发送/接收装置和通信装置，其实现容易地获取诊断结果和信号值，并进一步实现诊断结果的快速获取。根据本发明的信号监视装置（30）包括：差分值计算器（12），对于待监视的信号，对其信号值和预先设定的阈值之间的差值进行时间顺序的计算; 以及根据预先设定的规则更新并存储按时间顺序计算的差分值的存储器（13）。

3. 发明授权

US06677676B1 Semiconductor device having steady substrate potential 有权
标题翻译：半导体器件具有稳定的衬底电位
公开(公告)号：US06677676B1
公开(公告)日：2004-01-13
申请号：US09433382
申请日：1999-11-03
申请人： Yoshiki Wada , Kimio Ueda
发明人： Yoshiki Wada , Kimio Ueda
IPC分类号： H01L2348
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.
摘要翻译：一种具有SOI结构的半导体器件，具有用于使半导体衬底的电位稳定的接点，而不会增加半导体器件的表面。在半导体芯片中，在内部电路区域内制造集成电路，并且在缓冲区域内制造多个缓冲电路。在除了内部电路区域和缓冲区域之外的半导体芯片的区域中形成用于提供稳定电位的布线层; 例如在半导体芯片的四个角部，并且在不用于集成电路的制造的集成电路的区域中形成用于连接布线层和半导体基板的触点，因此不需要特别地确保位置分配用于形成联系人。

4. 发明授权

US06500722B2 Inductor recognition method, layout inspection method, computer readable recording medium in which a layout inspection program is recorded and process for a semiconductor device 失效
公开(公告)号：US06500722B2
公开(公告)日：2002-12-31
申请号：US09951427
申请日：2001-09-14
申请人： Yoshiki Wada , Hiroshi Komurasaki , Shigenobu Maeda , Shuji Yoshida
发明人： Yoshiki Wada , Hiroshi Komurasaki , Shigenobu Maeda , Shuji Yoshida
IPC分类号： H01L2120
CPC分类号： H01L23/5227 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An inductor recognition method for recognizing an inductor, a layout inspection method wherein it is possible to automatically carry out a verification of a design standard, in the inductor and a process for a semiconductor device using this layout inspection method are provided. The inductor recognition method includes the step of arranging an inductor position representation mark so as to surround a design pattern of an interconnection part, which works as an inductor and has a starting point and a finishing point; the step of arranging a starting point position representation mark and a finishing point position representation mark so as to surround, respectively, regions corresponding to the starting point and the finishing point; and the step of recognizing information with respect to an inductor by means of the inductor position representation mark, the starting point position representation mark and the finishing point position representation mark.

5. 发明授权

US06433620B1 Silicon-on-insulator CMOS circuit 有权
标题翻译：绝缘体上硅CMOS电路
公开(公告)号：US06433620B1
公开(公告)日：2002-08-13
申请号：US09716260
申请日：2000-11-21
申请人： Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
发明人： Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
IPC分类号： H03K190948
CPC分类号： H03K19/0027 , H03K19/01707 , H03K2217/0018
摘要： A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.
摘要翻译：绝缘体上硅绝缘体（SOI）CMOS电路包括彼此串联连接的多个PMOS晶体管和连接到PMOS晶体管之一的至少一个NMOS晶体管。 NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还包括体电位发生电路，其产生高参考电位和通过从高参考电位减去内置电位而获得的电位之间的体电位。体电位产生电路将高电位施加到PMOS晶体管的主体。

6. 发明授权

US06242786B1 SOI Semiconductor device with field shield electrode 失效
标题翻译：具有场屏蔽电极的SOI半导体器件
公开(公告)号：US06242786B1
公开(公告)日：2001-06-05
申请号：US09213280
申请日：1998-12-17
申请人： Yoshiki Wada , Hirotada Kuriyama , Kimio Ueda , Koichiro Mashiko , Hiroaki Suzuki
发明人： Yoshiki Wada , Hirotada Kuriyama , Kimio Ueda , Koichiro Mashiko , Hiroaki Suzuki
IPC分类号： H01L2940
CPC分类号： H01L21/76264 , H01L21/76291 , H01L27/1203
摘要： A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.
摘要翻译：形成由一种晶体管组成的场屏蔽部分，以将存储器单元的NMOS区域与其他区域电绝缘。场屏蔽部分包括场屏蔽栅极电极层，p型区域和栅极绝缘膜。该晶体管的阈值被设定为高于电源电压，并且其栅极电极层处于浮置状态。不需要在场屏蔽栅电极层设置用于施加规定电压的接触部。因此，可以减小在场屏蔽栅电极层中形成接触部分的区域。结果，提供了一种其布局面积减小的半导体器件。

7. 发明授权

US6084255A Gate array semiconductor device 失效
标题翻译：门阵列半导体器件
公开(公告)号：US6084255A
公开(公告)日：2000-07-04
申请号：US126092
申请日：1998-07-30
申请人： Kimio Ueda , Takanori Hirota , Yoshiki Wada , Koichiro Mashiko
发明人： Kimio Ueda , Takanori Hirota , Yoshiki Wada , Koichiro Mashiko
IPC分类号： H01L21/82 , H01L27/02 , H01L27/118 , H01L27/12 , H01L27/10
CPC分类号： H01L27/0207 , H01L27/11807 , H01L27/1203
摘要： In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption. Further, with positional relation between the body contact regions (9), (10) and the gate contact regions (5), (7), the device is capable of freely setting the transistors to be of either a gate control type or a gate fixed type. As a result, the gate array type semiconductor device achieves high-speed operation and low power consumption.
摘要翻译：在以SOI阵列排列的每个基本单元（BC）中，对称地形成PMOS和NMOS晶体管。主体区域（11）和（12）分别形成为分隔源极/漏极层（1）和（2），并且在主体区域（11）和（12）上形成栅电极（3）和（4）分别在其间夹着栅极绝缘膜。栅电极（3）和（4）的两端分别连接到栅极接触区域（5）至（8），并且主体区域（11）和（12）在其一端连接到主体接触区域（9）和（10）。主体接触区域（9）和（10）被布置成分别将栅极接触区域（5）和（7）与栅极电极（3）和（4）夹在一起。作为SOI型，该器件实现了高速操作和低功耗。此外，通过体接触区域（9），（10）和栅极接触区域（5），（7）之间的位置关系，该器件能够自由地将晶体管设置为栅极控制型或栅极固定式。结果，门阵列型半导体器件实现了高速操作和低功耗。

8. 发明授权

US06518790B2 Semiconductor integrated circuit having circuit for transmitting input signal 有权
公开(公告)号：US06518790B2
公开(公告)日：2003-02-11
申请号：US09940622
申请日：2001-08-29
申请人： Yoshiki Wada , Harufusa Kondoh
发明人： Yoshiki Wada , Harufusa Kondoh
IPC分类号： H03K190175
CPC分类号： H01L27/088 , H03K5/151
摘要： A semiconductor integrated circuit includes inverters and a PMOS transistor which are disposed for a first signal, and inverters and a PMOS transistor which are disposed for a second signal substantially complementary to the first signal. By the transistors, potentials of signal lines are driven. A transistor for 1.8 V is used for each of the transistors and the inverters at the rear stage. A transistor for 3.3 V is used for each of the inverters at the front stage. With the configuration, the complementary signals are transmitted at optimum timings.

9. 发明授权

US06177826B1 Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate 失效
标题翻译：具有串联连接的PMOS晶体管的绝缘体上硅电路，每个具有连接体和栅极
公开(公告)号：US06177826B1
公开(公告)日：2001-01-23
申请号：US09053700
申请日：1998-04-02
申请人： Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
发明人： Koichiro Mashiko , Kimio Ueda , Yoshiki Wada
IPC分类号： H03K190948
CPC分类号： H03K19/0027 , H03K19/01707 , H03K2217/0018
摘要： A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.
摘要翻译：绝缘体上硅绝缘体（SOI）CMOS电路包括彼此串联连接的多个PMOS晶体管，多个PMOS晶体管中的每一个具有彼此连接的主体和栅极，以及连接到一个的至少一个NMOS晶体管的NMOS晶体管，其NMOS晶体管的主体连接到具有接地值的低参考电位。 SOI CMOS电路还可以包括多个限制电路，每个电位限制电路连接在多个PMOS晶体管中的每一个的主体和栅极之间，用于将多个PMOS晶体管的每个的主体的电位的下限设置为通过从高参考电位减去内置电位而获得的高参考电位和电位之间的电压。

10. 发明授权

US5994935A Latch circuit and flip-flop circuit reduced in power consumption 有权
标题翻译：锁存电路和触发器电路功耗降低
公开(公告)号：US5994935A
公开(公告)日：1999-11-30
申请号：US130607
申请日：1998-08-07
申请人： Kimio Ueda , Koichiro Mashiko , Yoshiki Wada
发明人： Kimio Ueda , Koichiro Mashiko , Yoshiki Wada
IPC分类号： H03K3/037 , H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/356156
摘要： A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.
摘要翻译：触发器电路由级联的相同结构的两个锁存电路构成。锁存电路各自包括由P沟道晶体管和N沟道晶体管形成的反相器，连接在公共节点和接地节点之间的N沟道晶体管，以及两个数据输入/输出端子。提供给N沟道晶体管的栅极的两种时钟信号彼此互补。

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