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1. 发明授权

US06427205B1 Digital signal processor and processor reducing the number of instructions upon processing condition execution instructions 失效
标题翻译：数字信号处理器和处理器在处理条件执行指令时减少指令数量
公开(公告)号：US06427205B1
公开(公告)日：2002-07-30
申请号：US09342266
申请日：1999-06-29
申请人： Koichi Mori , Toshiyuki Furusawa , Daisuke Sonoda
发明人： Koichi Mori , Toshiyuki Furusawa , Daisuke Sonoda
IPC分类号： G06F938
CPC分类号： G06F9/3867 , G06F9/3842
摘要： In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a register (A) is put on a data bus assuming the condition is consistent when a condition execution instruction is decoded in an instruction decoder (14). Then, in the instruction execution cycle of the condition execution instruction, a register (B) introduced the value on the data bus when upon consistency of the condition. As a result, even before a condition flag (Z) changes as a result of execution of the instruction for generating the condition in the instruction execution cycle, the condition execution instruction can be decoded. Thus, the processor may omit an instruction other than “condition generation instruction or condition execution instruction” which was conventionally required.
摘要翻译：在用于流水线处理的数字信号处理器中，分为至少三个步骤，即指令提取周期，指令解码周期和指令执行周期，寄存器（A）的值放在数据总线上，假设条件是一致的，当a 条件执行指令在指令解码器（14）中解码。然后，在条件执行指令的指令执行周期中，当条件一致时，寄存器（B）将该值引入数据总线上。结果，即使在条件标志（Z）作为执行用于在指令执行周期中生成条件的指令的结果而变化的情况下，可以对条件执行指令进行解码。因此，处理器可以省略除常规要求的“条件生成指令或条件执行指令”之外的指令。

2. 发明授权

US07109771B2 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US07109771B2
公开(公告)日：2006-09-19
申请号：US10946398
申请日：2004-09-21
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H03K3/356
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

3. 发明申请

US20050035803A1 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US20050035803A1
公开(公告)日：2005-02-17
申请号：US10948349
申请日：2004-09-23
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K3/02
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

4. 发明授权

US06586982B2 Semiconductor circuit having a combination circuit being switched between an active and inactive state 失效
标题翻译：具有组合电路的半导体电路在有源和非活动状态之间切换
公开(公告)号：US06586982B2
公开(公告)日：2003-07-01
申请号：US09961027
申请日：2001-09-21
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H03K3037
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
摘要翻译：组合电路在响应于控制信号向其供电的有效状态和其中断电的无效状态之间切换。连接到组合电路的输入端的触发器电路响应于时钟信号存储组合电路的输出信号。组合电路通过紧接在触发器电路根据时钟信号工作之前的控制信号设置为工作状态。

5. 发明授权

US07088161B2 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US07088161B2
公开(公告)日：2006-08-08
申请号：US10948349
申请日：2004-09-23
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H03K3/356
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

6. 发明授权

US06861882B2 Semiconductor integrated circuit with reduced leakage current 失效
标题翻译：具有减小漏电流的半导体集成电路
公开(公告)号：US06861882B2
公开(公告)日：2005-03-01
申请号：US10342045
申请日：2003-01-14
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03L7/00
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.
摘要翻译：组合电路在响应于控制信号向其供电的有效状态和其中断电的无效状态之间切换。连接到组合电路的输入端的触发器电路响应于时钟信号存储组合电路的输出信号。组合电路通过紧接在触发器电路根据时钟信号工作之前的控制信号设置为工作状态。

7. 发明申请

US20050035802A1 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US20050035802A1
公开(公告)日：2005-02-17
申请号：US10946398
申请日：2004-09-21
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K3/02
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

8. 发明授权

US09128286B2 Display device and method for manufacturing the display device 有权
标题翻译：用于制造显示装置的显示装置和方法
公开(公告)号：US09128286B2
公开(公告)日：2015-09-08
申请号：US13429470
申请日：2012-03-26
申请人： Kouhei Takahashi , Takeshi Kuriyagawa , Daisuke Sonoda , Takuo Kaitoh , Katsumi Matsumoto
发明人： Kouhei Takahashi , Takeshi Kuriyagawa , Daisuke Sonoda , Takuo Kaitoh , Katsumi Matsumoto
IPC分类号： G02B26/02 , G09G3/34 , G02B26/08
CPC分类号： G02B26/02 , G02B26/0841 , G09G3/3433 , G09G2300/08
摘要： A metal layer is formed on a highly light-transmissive substrate; a resist mask having an opening pattern is formed on the metal layer; exposed portions of the metal layer is etched away in this state to form openings; then the resist mask is removed; and a surface of the metal layer and an inner side wall of each of the openings are oxidized to form a metal oxide layer. Thus, a front surface and a rear surface of the aperture plate are caused to have different reflectances. The oxide layer is formed at the same time as when the resist mask is ashed to remove resist.
摘要翻译：金属层形成在高透光性基板上; 在金属层上形成具有开口图案的抗蚀剂掩模; 在该状态下，金属层的暴露部分被蚀刻掉以形成开口; 然后去除抗蚀剂掩模; 并且金属层的表面和每个开口的内侧壁被氧化以形成金属氧化物层。因此，使孔板的前表面和后表面具有不同的反射率。在抗蚀剂掩模被灰化以除去抗蚀剂的同时形成氧化物层。

9. 发明申请

US20130021781A1 DISPLAY DEVICE WITH TAPERED LIGHT REFLECTING LAYER AND MANUFACTURING METHOD FOR SAME 有权
标题翻译：具有光束反射层的显示装置及其制造方法
公开(公告)号：US20130021781A1
公开(公告)日：2013-01-24
申请号：US13553527
申请日：2012-07-19
申请人： Daisuke Sonoda , Jun Fujiyoshi , Kohei Takahashi , Takuo Kaitou , Katsumi Matsumoto
发明人： Daisuke Sonoda , Jun Fujiyoshi , Kohei Takahashi , Takuo Kaitou , Katsumi Matsumoto
IPC分类号： G09F13/04 , B05D5/06 , B44C1/22 , G02B5/22
CPC分类号： G02B26/02 , G09G3/3433 , G09G2300/0426 , G09G2300/08
摘要： A display device includes a substrate having an upper surface. The display device also includes a light reflecting layer to reflect light, formed over the upper surface of the substrate. The display device also includes a light absorbing layer to absorb light, formed over the upper surface of the light reflecting layer. A plurality of apertures are defined through the light reflecting layer and the light absorbing layer such that, at an edge of each of the plurality of apertures, the light absorbing layer partially overhangs the light reflecting layer.
摘要翻译：显示装置包括具有上表面的基板。显示装置还包括形成在基板的上表面上的反射光的光反射层。显示装置还包括形成在光反射层的上表面上的吸收光的光吸收层。通过光反射层和光吸收层限定多个孔，使得在多个孔中的每一个的边缘处，光吸收层部分地悬垂在光反射层上。

10. 发明申请

US20100255643A1 METHOD FOR MANUFACTURING THIN-FILM TRANSISTORS 有权
标题翻译：制造薄膜晶体管的方法
公开(公告)号：US20100255643A1
公开(公告)日：2010-10-07
申请号：US12755584
申请日：2010-04-07
申请人： Hidekazu Nitta , Hidekazu Miyake , Takuo Kaitoh , Daisuke Sonoda
发明人： Hidekazu Nitta , Hidekazu Miyake , Takuo Kaitoh , Daisuke Sonoda
IPC分类号： H01L21/336 , H01L21/322
CPC分类号： H01L29/66765
摘要： Gate electrodes are formed on a substrate. A gate insulation film is formed so as to cover the gate electrodes. A semiconductor layer is formed in regions on the gate insulation film in a region which overlap with at least the gate electrodes. Plasma treatment is applied to the semiconductor layer using a gas which contains a dopant thus increasing impurity concentration of a surface layer of the semiconductor layer. A conductive film is formed on the surface layer of the semiconductor layer to which the plasma treatment is applied. A source electrode and a drain electrode are formed by etching the conductive film.
摘要翻译：栅电极形成在基板上。形成栅绝缘膜以覆盖栅电极。半导体层形成在与至少栅电极重叠的区域中的栅极绝缘膜上的区域中。使用包含掺杂剂的气体将等离子体处理施加到半导体层，从而增加半导体层的表面层的杂质浓度。在施加等离子体处理的半导体层的表面层上形成导电膜。通过蚀刻导电膜形成源电极和漏电极。

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