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1. 发明授权

US07170109B2 Heterojunction semiconductor device with element isolation structure 失效
标题翻译：具有元件隔离结构的异质结半导体器件
公开(公告)号：US07170109B2
公开(公告)日：2007-01-30
申请号：US10864457
申请日：2004-06-10
申请人： Kohei Sugihara , Kazunobu Ota , Hidekazu Oda , Takahashi Hayashi
发明人： Kohei Sugihara , Kazunobu Ota , Hidekazu Oda , Takahashi Hayashi
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L23/48
CPC分类号： H01L21/823481 , H01L21/76224 , H01L2924/0002 , H01L2924/00
摘要： A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench. Since the semiconductor film is interposed between the compound semiconductor film which is exposed by the trench and the first insulating film, there is no possibility that the compound semiconductor layer is directly thermally oxidized even if the semiconductor film is thermally oxidized to form the first insulating film.
摘要翻译：提供了能够提高半导体器件的元件隔离特性的技术。在其中硅层，化合物半导体层和半导体层依次层叠的半导体衬底中提供元件隔离结构。元件隔离结构由沟槽，半导体膜以及第一和第二绝缘膜构成。沟槽延伸穿过半导体层并延伸到化合物半导体层的内部。半导体膜设置在沟槽的表面上，第一绝缘膜设置在半导体膜上。第二绝缘膜设置在第一绝缘膜上并填充沟槽。由于半导体膜介于通过沟槽暴露的化合物半导体膜和第一绝缘膜之间，即使半导体膜被热氧化以形成第一绝缘膜，化合物半导体层也不可能直接热氧化。

2. 发明授权

US06963139B2 Semiconductor device including a layer having a β-crystal structure 失效
公开(公告)号：US06963139B2
公开(公告)日：2005-11-08
申请号：US10882256
申请日：2004-07-02
申请人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
发明人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the β-crystal structure.

3. 发明授权

US06617654B2 Semiconductor device with sidewall spacers and elevated source/drain region 失效
标题翻译：具有侧壁间隔件和升高的源极/漏极区域的半导体器件
公开(公告)号：US06617654B2
公开(公告)日：2003-09-09
申请号：US09955488
申请日：2001-09-19
申请人： Toshiyuki Oishi , Kohei Sugihara , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
发明人： Toshiyuki Oishi , Kohei Sugihara , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L2976
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/6656 , H01L29/7834
摘要： Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.
摘要翻译：源区和漏区包括在衬底的表面上的外延硅膜的区域和衬底中的区域。源极和漏极区域的结的深度与延伸区域的接合点的深度相同或更浅。结果，即使侧壁层的厚度减小，由于与源极和漏极区域相比，杂质浓度较低的延伸区域的耗尽层是主要的，所以短沟道效应具有较小的效果。

4. 发明申请

US20120153132A1 ELEMENT CARRIER AND LIGHT RECEIVING MODULE 审中-公开
标题翻译：元件运输车和灯光接收模块
公开(公告)号：US20120153132A1
公开(公告)日：2012-06-21
申请号：US13298702
申请日：2011-11-17
申请人： Yuichiro Horiguchi , Kohei Sugihara , Yasuhisa Shimakura , Toshiharu Miyahara , Satoshi Kajiya , Satoshi Nishikawa , Eiji Yagyu
发明人： Yuichiro Horiguchi , Kohei Sugihara , Yasuhisa Shimakura , Toshiharu Miyahara , Satoshi Kajiya , Satoshi Nishikawa , Eiji Yagyu
IPC分类号： H03F1/00 , H05K1/00
CPC分类号： G02B6/4274 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49433 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： An element carrier has a mounting surface where at least one element outputting a high-frequency signal is disposed. A first dielectric layer has a first side surface partially forming the mounting surface and a first main surface connecting to the first side surface and extending in an intersecting direction intersecting with the mounting surface. A first wiring pattern is provided on the first main surface and extends from the first side surface. A second dielectric layer has a second side surface partially forming the mounting surface and a second main surface connecting to the second side surface and extending in the intersecting direction, and is provided on a part of the first main surface of the first dielectric layer where the first wiring pattern is provided. A second wiring pattern is provided on the second main surface of the second dielectric layer and extends from the second side surface.
摘要翻译：元件载体具有其中设置有至少一个输出高频信号的元件的安装表面。第一电介质层具有部分地形成安装表面的第一侧表面和连接到第一侧表面并沿与安装表面相交的相交方向延伸的第一主表面。第一布线图案设置在第一主表面上并且从第一侧表面延伸。第二电介质层具有部分地形成安装面的第二侧面和与第二侧面连接并且在交叉方向上延伸的第二主表面，并且设置在第一电介质层的第一主表面的一部分上，提供第一布线图案。第二布线图案设置在第二介电层的第二主表面上并且从第二侧表面延伸。

5. 发明授权

US07015107B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07015107B2
公开(公告)日：2006-03-21
申请号：US10243742
申请日：2002-09-16
申请人： Kohei Sugihara , Hirokazu Sayama
发明人： Kohei Sugihara , Hirokazu Sayama
IPC分类号： H01L21/336
CPC分类号： H01L29/66492 , H01L29/41783 , H01L29/665 , H01L29/6653
摘要： When a dummy sidewall and source and drain regions are once formed and then the dummy sidewall is removed to extend the source and drain regions, the removal of the dummy sidewall is performed after formation of a protective oxide film on a gate electrode and on the major surfaces of the source and drain regions. This efficiently prevents conventional surface roughness of the upper surface of the gate electrode and the impurity region due to the removal of the dummy sidewall.
摘要翻译：当虚拟侧壁和源极和漏极区一旦形成，然后去除虚设侧壁以延伸源极和漏极区域时，在栅电极上形成保护氧化膜并在主电极上形成虚设侧壁的去除源区和漏区的表面。这有效地防止了由于去除虚设侧壁而导致的栅电极的上表面和杂质区域的常规表面粗糙度。

6. 发明申请

US20050035454A1 Semiconductor device including a layer having a beta-crystal structure 失效
标题翻译：包括具有β晶体结构的层的半导体器件
公开(公告)号：US20050035454A1
公开(公告)日：2005-02-17
申请号：US10882256
申请日：2004-07-02
申请人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
发明人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/532 , H01L29/04
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the β-crystal structure.
摘要翻译：在设置在半导体衬底上的绝缘或导电膜上形成阻挡层，并且在阻挡层上形成由导电膜制成的电极或互连。阻挡层包括具有β-晶体结构的钽膜。

7. 发明授权

US06770977B2 Semiconductor device and method for fabricating the same 失效
标题翻译：包括具有β晶体结构的层的半导体器件
公开(公告)号：US06770977B2
公开(公告)日：2004-08-03
申请号：US10036388
申请日：2002-01-07
申请人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
发明人： Takenobu Kishida , Shinya Tada , Atsushi Ikeda , Takeshi Harada , Kohei Sugihara
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the &bgr;-crystal structure.
摘要翻译：在设置在半导体衬底上的绝缘或导电膜上形成阻挡层，并且在阻挡层上形成由导电膜制成的电极或互连。阻挡层包括具有β-晶体结构的钽膜。

8. 发明授权

US06566734B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06566734B2
公开(公告)日：2003-05-20
申请号：US09809211
申请日：2001-03-16
申请人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
发明人： Kohei Sugihara , Toshiyuki Oishi , Naruhisa Miura , Yuji Abe , Yasunori Tokuda
IPC分类号： H01L29788
CPC分类号： H01L29/66651 , H01L29/1045 , H01L29/1054 , H01L29/66492 , H01L29/66545 , H01L29/66621
摘要： In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.
摘要翻译：在制作场效应晶体管时，在形成栅电极之前形成伪栅电极。相对于虚拟栅电极形成延伸区域，侧壁氮化硅膜，源极/漏极区域，氧化硅膜等元件。去除虚拟栅电极，并且去除扩散到虚拟栅电极正下方的区域中的一部分延伸区域。被去除的部分填充硅选择外延膜。之后，形成预定的栅电极。该制造方法产生场效应晶体管，其防止由短沟道效应和寄生电阻引起的电特性的劣化。

9. 发明授权

US06228728B1 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06228728B1
公开(公告)日：2001-05-08
申请号：US09243480
申请日：1999-02-03
申请人： Taisuke Furukawa , Takumi Nakahata , Shigemitsu Maruno , Kohei Sugihara , Yasutaka Nishioka , Satoshi Yamakawa , Yasunori Tokuda
发明人： Taisuke Furukawa , Takumi Nakahata , Shigemitsu Maruno , Kohei Sugihara , Yasutaka Nishioka , Satoshi Yamakawa , Yasunori Tokuda
IPC分类号： H01L21336
CPC分类号： H01L29/66628
摘要： According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.
摘要翻译：根据制造半导体器件的本发明方法，将硅衬底暴露于600℃至900℃的氧气氛中，以在外延硅层和硅片的表面上形成氧化硅膜。因此，可以提供一种制造能够防止其电极短路的半导体器件的方法。

10. 发明申请

US20120087653A1 OPTICAL TRANSMISSION APPARATUS AND OPTICAL TRANSMISSION METHOD 审中-公开
标题翻译：光传输装置和光传输方法
公开(公告)号：US20120087653A1
公开(公告)日：2012-04-12
申请号：US13378055
申请日：2010-03-08
申请人： Kazushige Sawada , Takashi Sugihara , Yasuhisa Shimakura , Kohei Sugihara
发明人： Kazushige Sawada , Takashi Sugihara , Yasuhisa Shimakura , Kohei Sugihara
IPC分类号： H04B10/04 , H04B10/08
CPC分类号： H04B10/516 , H04B10/5051
摘要： An optical transmission apparatus in which, even if a change is made in the bit rate of modulation signals that are inputted to a plurality of optical modulating units, the modulation signals do not suffer from phase shifting, thereby enabling achieving synchronous modulation in the plurality of optical modulating units and enabling achieving a high optical signal quality. The optical transmission apparatus includes: a plurality of optical modulating units that modulate light on the basis of modulation signals; and a delay amount control unit that, based on bit rate information indicating a bit rate of the modulation signals, controls delay amounts of the modulation signals to be inputted to the plurality of optical modulating units, such that the light is modulated in a synchronous manner in the plurality of optical modulating units.
摘要翻译：其中，即使在输入到多个光调制单元的调制信号的比特率中发生变化，调制信号也不会遭受相移，从而能够实现多个调制信号的同步调制光调制单元，实现高光信号质量。光传输装置包括：多个光调制单元，其基于调制信号调制光; 以及延迟量控制单元，其基于表示调制信号的比特率的比特率信息，控制要输入到多个光调制单元的调制信号的延迟量，使得以同步方式调制光在多个光学调制单元中。

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