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1. 发明授权

US06588002B1 Method and system for predictive layout generation for inductors with reduced design cycle 有权
标题翻译：减少设计周期的电感器的预测布局生成方法和系统
公开(公告)号：US06588002B1
公开(公告)日：2003-07-01
申请号：US09941883
申请日：2001-08-28
申请人： Koen Lampaert , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya , Francis M Rotella , Rajesh Divecha
发明人： Koen Lampaert , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya , Francis M Rotella , Rajesh Divecha
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/5063
摘要： In one embodiment, a number of parameter values for an inductor, such as a spiral inductor, are received. Examples of the parameter values are Number of Turns, Spacing, Width, Xsize, and Ysize parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the inductor are determined. For example, parasitic resistor values and parasitic capacitor values of the inductor are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the inductor. An inductor layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the inductor. As such, the parasitic values of the inductor have already been taken into account in the initial circuit simulation and, there is no need to extract the internal parasitics of the inductor for further circuit simulations.
摘要翻译：在一个实施例中，接收诸如螺旋电感器的电感器的多个参数值。参数值的示例是Turns，Spacing，Width，Xsize和Ysize参数值。从接收到的参数值中，确定电感器的子电路模型的寄生值的数量。例如，确定电感器的寄生电阻值和寄生电容值。寄生电阻值和寄生电容值用于模拟包括电感的电路。然后产生电感器布局，其产生与在模拟包括电感器的电路中已经使用的寄生值相同的寄生值。因此，在初始电路仿真中已经考虑了电感器的寄生值，并且不需要提取电感器的内部寄生效应用于进一步的电路仿真。

2. 发明授权

US06728942B2 Method and system for predictive MOSFET layout generation with reduced design cycle 有权
标题翻译：减少设计周期的预测MOSFET布局生成方法和系统
公开(公告)号：US06728942B2
公开(公告)日：2004-04-27
申请号：US09879142
申请日：2001-06-12
申请人： Koen Lampaert , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya
发明人： Koen Lampaert , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style, bulk contact, finger width, finger length, number of fingers, current, and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.
摘要翻译：在一个公开的实施例中，接收RF MOSFET的多个参数值。参数值的示例是样式，批量接触，手指宽度，手指长度，手指数，当前和切片参数值。根据接收的参数值，确定RF MOSFET的子电路模型的寄生数值。例如，确定RF MOSFET的寄生电阻值和寄生电容值。寄生电阻值和寄生电容值用于模拟包括RF MOSFET的电路。然后产生RF MOSFET布局，其导致寄生值与在模拟包括RF MOSFET的电路中已经使用的寄生值相同。因此，在初始电路仿真中已经考虑了RF MOSFET的寄生值。

3. 发明授权

US06839887B1 Method and system for predictive multi-component circuit layout generation with reduced design cycle 有权
标题翻译：具有减少设计周期的预测多组件电路布局生成方法和系统
公开(公告)号：US06839887B1
公开(公告)日：2005-01-04
申请号：US10029476
申请日：2001-10-24
申请人： Koen Lampaer , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya
发明人： Koen Lampaer , Andy Brotman , Paolo Miliozzi , Paramjit Singh , Mishel Matloubian , Bijan Bhattacharyya
IPC分类号： G06F9/45 , G06F9/455 , G06F17/50
CPC分类号： G06F17/5063
摘要： One embodiment discloses receiving a number of parameter values for a multi-component circuit. From the received parameter values, a number of parasitic values for various components in the multi-component circuit are determined. For example, parasitic resistor values and parasitic capacitor values for transistors in the multi-component circuit are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the multi-component circuit. According to a disclosed embodiment, a layout of the multi-component circuit is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the multi-component circuit. As such, the parasitic values of the multi-component circuit have already been taken into account in the initial circuit simulation and there is no need to extract the internal parasitics of the multi-component circuit for further circuit simulations.
摘要翻译：一个实施例公开了接收多组件电路的多个参数值。从接收到的参数值中，确定多组分电路中的各种组件的寄生值的数量。例如，确定多组分电路中的晶体管的寄生电阻值和寄生电容值。寄生电阻值和寄生电容值用于模拟多分量电路。根据所公开的实施例，然后产生多分量电路的布局，其导致与模拟多分量电路中已经使用的寄生值相同的寄生值。因此，在初始电路仿真中已经考虑了多分量电路的寄生值，并且不需要提取用于进一步电路仿真的多分量电路的内部寄生效应。

4. 发明授权

US06518604B1 Diode with variable width metal stripes for improved protection against electrostatic discharge (ESD) current failure 有权
标题翻译：具有可变宽度金属条纹的二极管，用于改善针对静电放电（ESD）电流故障的保护
公开(公告)号：US06518604B1
公开(公告)日：2003-02-11
申请号：US09667364
申请日：2000-09-21
申请人： Eugene R. Worley , Mishel Matloubian
发明人： Eugene R. Worley , Mishel Matloubian
IPC分类号： H01L2974
CPC分类号： H01L27/0255 , H01L29/417 , H01L29/8611
摘要： A diode for improved electrostatic discharge (ESD) protection against current failure includes a plurality of elongate anode and cathode conductor stripes each having first and second end portions of different widths to reduce current densities at feeder bus tie points, thereby reducing the possibility of current failure.
摘要翻译：用于改善针对电流故障的静电放电（ESD）保护的二极管包括多个细长的阳极和阴极导体条，每个具有不同宽度的第一和第二端部以减小馈线总线连接点处的电流密度，从而减少电流故障的可能性。

5. 发明授权

US4753896A Sidewall channel stop process 失效
标题翻译：侧壁通道停止过程
公开(公告)号：US4753896A
公开(公告)日：1988-06-28
申请号：US933500
申请日：1986-11-21
申请人： Mishel Matloubian
发明人： Mishel Matloubian
IPC分类号： H01L27/12 , H01L21/762 , H01L21/84 , H01L21/86 , H01L29/786 , H01L21/225 , H01L21/308
CPC分类号： H01L21/76264 , H01L21/76224 , H01L21/84 , H01L21/86 , H01L21/76283 , H01L21/76289
摘要： A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.
摘要翻译：硅绝缘体器件（包括氧化硅，氮化硅和蓝宝石器件上的硅）制作侧壁通道的新方式。当护壁区域11,13（其中将形成有源器件）被厚掩模材料24覆盖时，高能量注入步骤将额外的掺杂引入暴露的硅区域14'。在执行台面蚀刻以隔离各个有源器件区域32之前，在覆盖有源器件区域32的预定位置的掩模材料24的壁上形成细丝28.然后使用化学物质进行台面蚀刻不仅被原始掩模材料24阻挡，而且被侧壁细丝28阻挡。因此，通过注入到区域14'中限定的掺杂水平将延伸到台面32的侧壁中一段距离，该距离不仅由侧向这些掺杂剂的扩散长度，也是侧壁丝28的厚度。

6. 发明授权

US5026656A MOS transistor with improved radiation hardness 失效
标题翻译：具有改善辐射硬度的MOS晶体管
公开(公告)号：US5026656A
公开(公告)日：1991-06-25
申请号：US488360
申请日：1990-03-02
申请人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
发明人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
IPC分类号： H01L21/74 , H01L23/482 , H01L29/786
CPC分类号： H01L23/4825 , H01L21/743 , H01L29/78609 , H01L29/78612 , H01L2924/0002 , Y10S438/953
摘要： An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.
摘要翻译：公开了一种MOS晶体管，其具有用于在暴露于电离辐射之后通过隔离氧化物防止源极至漏极导通的保护环。在所描述的n沟道晶体管的例子中，相对于栅电极以自对准的方式在源极区域的边缘处形成p +区域，以便不在栅极下方延伸以接触漏极区域。即使在栅电极与场氧化物重叠的隔离场氧化物下面形成沟道，该p +区形成二极管，其阻止源 - 漏导通。该结构可以被硅化以提高串联电阻。还公开了以SOI配置形成的晶体管的示例。

7. 发明授权

US5399519A Method of manufacturing semiconductor on insulator transistor with complementary transistor coupled to the channel 失效
标题翻译：制造具有耦合到沟道的互补晶体管的半导体绝缘体晶体管的方法
公开(公告)号：US5399519A
公开(公告)日：1995-03-21
申请号：US76599
申请日：1993-06-14
申请人： Mishel Matloubian
发明人： Mishel Matloubian
IPC分类号： H01L27/088 , H01L21/335
CPC分类号： H01L27/088
摘要： The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor. In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor's channel.
摘要翻译：本发明的所描述的实施例提供了一种用于主动控制施加到场效应晶体管的沟道的电压的方法和结构。在所描述的实施例中，制造了连接到沟道区的晶体管。沟道晶体管与使用主沟道区的晶体管具有相反的导电类型。沟道晶体管的源极连接到沟道，沟道晶体管的漏极连接到参考电压。相同的栅极用于控制沟道晶体管和主晶体管。当施加导致主晶体管导通的电压时，沟道晶体管截止，从而允许沟道浮动并允许更高的驱动电流。另一方面，当施加关闭主晶体管的电压时，沟道晶体管导通，从而将沟道区夹持到参考电压。这允许主晶体管的一致的阈值电压控制。在优选实施例中，主晶体管的沟道用作沟道晶体管的源极，并且主晶体管的栅极延伸到沟道晶体管的沟道区上。参考电压然后连接到形成在沟道晶体管沟道区域与主晶体管沟道的相对侧上的漏极区域。

8. 发明授权

US5144390A Silicon-on insulator transistor with internal body node to source node connection 失效
标题翻译：具有内部节点到源节点连接的硅上绝缘体晶体管
公开(公告)号：US5144390A
公开(公告)日：1992-09-01
申请号：US663190
申请日：1991-02-28
申请人： Mishel Matloubian
发明人： Mishel Matloubian
IPC分类号： H01L21/336 , H01L27/07 , H01L29/10 , H01L29/786
CPC分类号： H01L29/66772 , H01L27/0727 , H01L29/1083 , H01L29/78612
摘要： A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed by implant and diffusion under the n+ source region, the p+ region in contact on one end with the relatively lightly doped p-type body node. The relatively high dopant concentration of both the p+ region and the n+ source region creates a tunnel diode. The tunnel diode conducts with very low forward voltages, which causes the body node region to be substantially biased to the potential of the source region. Methods for forming the transistor are also disclosed, including the use of a source/drain anneal prior to p-type implant, or alternatively a second sidewall oxide filament, to preclude the boron from counterdoping the LDD extension at the source side. Both silicon-on-insulator and bulk embodiments are disclosed.
摘要翻译：公开了晶体管和制造晶体管的方法，其中形成隧道二极管以在晶体管的源极和栅极之下的体节点之间形成连接。对于n沟道晶体管的示例，通过在n +源极区域下的注入和扩散形成p +区域，在一端与相对轻掺杂的p型体节点接触的p +区域。 p +区域和n +源极区域的相对高的掺杂剂浓度产生隧道二极管。隧道二极管以非常低的正向电压导通，这导致体节点区域基本上偏置到源极区域的电位。还公开了用于形成晶体管的方法，包括在p型注入之前使用源极/漏极退火，或者替代地使用第二侧壁氧化物细丝，以阻止硼反向掺杂源极侧的LDD延伸。公开了绝缘体上硅和体实施例。

9. 发明授权

US4974051A MOS transistor with improved radiation hardness 失效
标题翻译：具有改善辐射硬度的MOS晶体管
公开(公告)号：US4974051A
公开(公告)日：1990-11-27
申请号：US150799
申请日：1988-02-01
申请人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
发明人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
IPC分类号： H01L21/76 , H01L21/74 , H01L23/482 , H01L27/10 , H01L29/78 , H01L29/786
CPC分类号： H01L23/4825 , H01L21/743 , H01L29/78609 , H01L29/78612 , H01L2924/0002
摘要： An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.
摘要翻译：公开了一种MOS晶体管，其具有用于在暴露于电离辐射之后通过隔离氧化物防止源极至漏极导通的保护环。在所描述的n沟道晶体管的例子中，相对于栅电极以自对准的方式在源极区域的边缘处形成p +区域，以便不在栅极下方延伸以接触漏极区域。即使在栅电极与场氧化物重叠的隔离场氧化物下面形成沟道，该p +区形成二极管，其阻止源 - 漏导通。该结构可以被硅化以提高串联电阻。还公开了以SOI配置形成的晶体管的示例。

10. 发明授权

US4950618A Masking scheme for silicon dioxide mesa formation 失效
标题翻译：二氧化硅台面形成掩蔽方案
公开(公告)号：US4950618A
公开(公告)日：1990-08-21
申请号：US338719
申请日：1989-04-14
申请人： Ravishankar Sundaresan , Mishel Matloubian
发明人： Ravishankar Sundaresan , Mishel Matloubian
IPC分类号： H01L21/033 , H01L21/266
CPC分类号： H01L21/266 , H01L21/033 , Y10S148/053 , Y10S148/082
摘要： An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).
摘要翻译：改进的掩模叠层（63）包括衬垫氧化物（58），多晶硅（60）和氮化物（62）。在堆叠（63）上形成光致抗蚀剂图案（64）之后，进行各向异性蚀刻以除去未被图案（64）覆盖的氮化物（62）和多晶硅（60）的一部分。执行另一蚀刻以去除剩余的多晶硅（60）以留下衬垫氧化物（58）的至少一部分。导电硼植入物（66）在未掩模的硅有源器件层（56）内形成植入区域（68和70）。植入区域（68和70）的一部分用氮化物（72）掩蔽，然后对未掩模的硅层（56）进行蚀刻。除去掩蔽堆叠（63）和氮化物（72），并且用形成二氧化硅台面（78）的氧化物覆盖未保护的硅层（56）和植入区域（68和70）。

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