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1. 发明申请

US20090200533A1 Resistive Memory Element and Method of Fabrication 失效
标题翻译：电阻记忆元件及其制作方法
公开(公告)号：US20090200533A1
公开(公告)日：2009-08-13
申请号：US12028513
申请日：2008-02-08
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , H01L27/222 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/149 , H01L45/1625 , H01L45/1675
摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
摘要翻译：描述了包括存储单元的集成电路和集成电路的制造方法。存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。电阻性存储元件基于电阻式存储元件的电阻率存储信息。

2. 发明授权

US07538411B2 Integrated circuit including resistivity changing memory cells 失效
标题翻译：集成电路包括电阻率变化记忆单元
公开(公告)号：US07538411B2
公开(公告)日：2009-05-26
申请号：US11411994
申请日：2006-04-26
申请人： Josef Willer , Klaus-Dieter Ufert
发明人： Josef Willer , Klaus-Dieter Ufert
IPC分类号： H01L29/00
CPC分类号： H01L45/14 , B82Y10/00 , G11C13/00 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C2213/32 , H01L27/2436 , H01L27/2472 , H01L45/04 , H01L45/1226 , H01L45/145 , H01L45/146 , H01L45/1675 , H01L45/1683
摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.
摘要翻译：字线堆叠在衬底表面上彼此间隔一定距离平行排列。位线横向于彼此间隔一定距离的字线堆栈布置。源极/漏极区域形成为字线堆叠附近的掺杂区域。电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

3. 发明申请

US20070254428A1 INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MEMORY CELLS 失效
标题翻译：集成电路，包括电阻变化记忆细胞
公开(公告)号：US20070254428A1
公开(公告)日：2007-11-01
申请号：US11411994
申请日：2006-04-26
申请人： Josef Willer , Klaus-Dieter Ufert
发明人： Josef Willer , Klaus-Dieter Ufert
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L45/14 , B82Y10/00 , G11C13/00 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C2213/32 , H01L27/2436 , H01L27/2472 , H01L45/04 , H01L45/1226 , H01L45/145 , H01L45/146 , H01L45/1675 , H01L45/1683
摘要： Wordline stacks are arranged parallel at a distance from one another on a substrate surface. Bitlines are arranged transversely to the wordline stacks at a distance from one another. Source/drain regions are formed as doped regions in the vicinity of the wordline stacks. A resistive layer is disposed between a plurality of the source/drain regions and the bitlines and formed of a material having a resistance that is switched by an applied voltage. Source lines are arranged parallel to the wordline stacks so that they connect further pluralities of the source/drain regions.
摘要翻译：字线堆叠在衬底表面上彼此间隔一定距离平行排列。位线横向于彼此间隔一定距离的字线堆栈布置。源极/漏极区域形成为字线堆叠附近的掺杂区域。电阻层设置在多个源极/漏极区域和位线之间，并且由具有通过施加电压切换的电阻的材料形成。源极线平行于字线堆栈布置，使得它们连接更多个源极/漏极区域。

4. 发明申请

US20090272958A1 Resistive Memory 审中-公开
标题翻译：电阻记忆
公开(公告)号：US20090272958A1
公开(公告)日：2009-11-05
申请号：US12114480
申请日：2008-05-02
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233
摘要： An integrated circuit including a memory cell and method of manufacturing the integrated circuit are described. The memory cell includes a diode and a resistive memory element coupled to the diode. The resistive memory element includes a thin oxide storage layer that uses multiple resistance levels to store more than one bit of information in the resistive memory element.
摘要翻译：描述了包括存储单元的集成电路及其制造方法。存储单元包括耦合到二极管的二极管和电阻存储元件。电阻性存储元件包括薄的氧化物存储层，其使用多个电阻电平在电阻存储元件中存储多于一位的信息。

5. 发明授权

US07741630B2 Resistive memory element and method of fabrication 失效
标题翻译：电阻记忆元件及其制造方法
公开(公告)号：US07741630B2
公开(公告)日：2010-06-22
申请号：US12028513
申请日：2008-02-08
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/222 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/149 , H01L45/1625 , H01L45/1675
摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.
摘要翻译：描述了包括存储单元的集成电路和集成电路的制造方法。存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。电阻性存储元件基于电阻式存储元件的电阻率存储信息。

6. 发明申请

US20080029803A1 Programmable non-volatile memory cell 审中-公开
标题翻译：可编程非易失性存储单元
公开(公告)号：US20080029803A1
公开(公告)日：2008-02-07
申请号：US11497528
申请日：2006-08-02
申请人： Klaus Dieter Ufert , Josef Willer , David Abookasis
发明人： Klaus Dieter Ufert , Josef Willer , David Abookasis
IPC分类号： H01L29/788
CPC分类号： H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1226
摘要： The present invention relates to a reprogrammable non-volatile memory cell which comprises a selection transistor and a data storage element. The invention further relates to a method of fabricating such a memory cell, as well as to a memory cell array comprising a number of such memory cells.
摘要翻译：本发明涉及一种可编程非易失性存储单元，其包括选择晶体管和数据存储元件。本发明还涉及一种制造这种存储单元的方法，以及包括许多这种存储单元的存储单元阵列。

7. 发明授权

US07312491B2 Charge trapping semiconductor memory element with improved trapping dielectric 有权
标题翻译：电荷捕获半导体存储元件具有改进的俘获电介质
公开(公告)号：US07312491B2
公开(公告)日：2007-12-25
申请号：US11359783
申请日：2006-02-23
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L27/108
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/513 , H01L29/792
摘要： A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.
摘要翻译：可以通过场效应控制的半导体存储元件包括：第一导电类型的半导体衬底;设置在半导体衬底中的第二导电类型的第一掺杂区;第二导电类型的第二掺杂区; 半导体衬底，位于第一和第二掺杂区域之间的沟道区，与沟道区相邻布置并具有电荷俘获存储层的多层栅极电介质和设置在栅极电介质上方的栅极端子。电荷捕获存储层包括至少一个相邻层序列，其中相邻层的序列包括非晶碳化硅层和非晶氮化硅层。

8. 发明申请

US20060197141A1 Charge trapping semiconductor memory element with improved trapping dielectric 有权
标题翻译：电荷捕获半导体存储元件具有改进的俘获电介质
公开(公告)号：US20060197141A1
公开(公告)日：2006-09-07
申请号：US11359783
申请日：2006-02-23
申请人： Klaus-Dieter Ufert , Josef Willer
发明人： Klaus-Dieter Ufert , Josef Willer
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/513 , H01L29/792
摘要： A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.
摘要翻译：可以通过场效应控制的半导体存储元件包括：第一导电类型的半导体衬底;设置在半导体衬底中的第二导电类型的第一掺杂区;第二导电类型的第二掺杂区; 半导体衬底，位于第一和第二掺杂区域之间的沟道区，与沟道区相邻布置并具有电荷俘获存储层的多层栅极电介质和设置在栅极电介质上方的栅极端子。电荷捕获存储层包括至少一个相邻层序列，其中相邻层的序列包括非晶碳化硅层和非晶氮化硅层。

9. 发明申请

US20100019345A1 Integrated Circuit with an Active Area Line Having at Least One Form-Supporting Element and Corresponding Method of Making an Integrated Circuit 有权
标题翻译：具有至少一个支撑元件的有源面积线的集成电路和制造集成电路的相应方法
公开(公告)号：US20100019345A1
公开(公告)日：2010-01-28
申请号：US12177930
申请日：2008-07-23
申请人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
发明人： Josef Willer , Michael Specht , Christoph Friederich , Doris Keitel-Schulz
IPC分类号： H01L21/3065 , H01L23/58
CPC分类号： H01L21/28273 , H01L21/3086 , H01L21/32139 , H01L27/0207 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： An integrated circuit is described. The integrated circuit may have: an active area line formed of a material of a semiconductor substrate with a first longitudinal direction parallel to an upper surface of the semiconductor substrate; wherein the active area line has at least one form-supporting element extending in a second longitudinal direction parallel to the upper surface of the semiconductor substrate; and wherein the second longitudinal direction is arranged with regard to the first longitudinal direction in an angle unequal to 0 degree and unequal to 180 degree.
摘要翻译：描述了集成电路。集成电路可以具有：由具有与半导体衬底的上表面平行的第一纵向方向的半导体衬底的材料形成的有源区线; 其中所述有源面积线具有至少一个形状支撑元件，所述支撑元件在平行于所述半导体衬底的上表面的第二纵向方向上延伸; 并且其中所述第二纵向方向相对于所述第一纵向方向以不等于0度并且不等于180度的角度布置。

10. 发明申请

US20090261397A1 Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method 有权
标题翻译：具有过渡金属的浮栅电极集成电路及相应的制造方法
公开(公告)号：US20090261397A1
公开(公告)日：2009-10-22
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译：描述了集成电路。集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个浮栅电极包括过渡金属。还描述了集成电路的相应制造方法。

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